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1.发明授权Circuit for converting a logic signal on an output node to a pair of low-voltage differential signals 有权用于将输出节点上的逻辑信号转换成一对低压差分信号的电路公开(公告)号：US06353334B1
公开(公告)日：2002-03-05
申请号：US09492560
申请日：2000-01-27
IPC分类号： H03K190185
CPC分类号： H03K19/017545
摘要： Described are a system and method for converting a typical two-level logic signal to a pair of differential logic signals. In accordance with one embodiment, a field programmable gate array (FPGA) is configured to provide a digital signal and its complement on a pair of output terminals. A resistor network connected to these output terminals converts the complementary signals to a pair of differential signals having current and voltage levels within the range established by the LVDS specification. For maximum efficiency, the values of the resistors that make up the resistor network can be selected to match the 100 ohm input resistance exhibited by LVDS receivers.
摘要翻译： 描述了将典型的两级逻辑信号转换成一对差分逻辑信号的系统和方法。 根据一个实施例，现场可编程门阵列（FPGA）被配置为在一对输出端子上提供数字信号及其补码。 连接到这些输出端子的电阻网络将互补信号转换成具有由LVDS规范建立的范围内的电流和电压电平的一对差分信号。 为了获得最大的效率，可以选择构成电阻网络的电阻值与LVDS接收机所表现的100欧姆输入电阻相匹配。
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2.发明授权公开(公告)号：US08225187B1
公开(公告)日：2012-07-17
申请号：US12059773
申请日：2008-03-31
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： A cyclic redundancy check (CRC) bit-slice circuit including a plurality of AND gates coupled with configuration data is described. The configuration data may enable the plurality of AND gates to provide a set of CRC input data and feedback polynomial data meeting a plurality of CRC protocols. The CRC bit-slice circuit accepts a generator polynomial as an input design parameter to build a CRC module. The modularity of the design then allows a larger CRC design to be constructed from multiple CRC modules such that wider data width may be accommodated. Several CRC modules can be cascaded to accommodate various data widths and to meet a plurality of CRC protocols.
摘要翻译： 描述了包括与配置数据耦合的多个与门的循环冗余校验（CRC）位片电路。 配置数据可以使得多个与门能够提供满足多个CRC协议的一组CRC输入数据和反馈多项式数据。 CRC位片电路接受生成多项式作为输入设计参数来构建CRC模块。 因此，设计的模块化允许从多个CRC模块构建更大的CRC设计，从而可以容纳更宽的数据宽度。 可以级联多个CRC模块以适应各种数据宽度并满足多个CRC协议。
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3.发明授权Method of and circuit for generating a random number using a multiplier oscillation 有权使用乘法器振荡产生随机数的方法和电路公开(公告)号：US08099449B1
公开(公告)日：2012-01-17
申请号：US11973040
申请日：2007-10-04
申请人： David P. Schultz
发明人： David P. Schultz
IPC分类号： G06F1/02
CPC分类号： G06F7/588 , H04L9/0866
摘要： A method of generating a random number using a multiplier oscillation, the method comprising providing a multiplier circuit coupled to receive a first digital input and a second digital input, wherein the first digital input and the second digital input are asynchronous signals and the first digital input comprises a feedback signal based upon an output of the multiplier circuit; allowing the multiplier to enter a state of feedback oscillation; and generating a random number based upon the output of the multiplier circuit. The method may further comprise providing a plurality of adders receiving feedback signals.
摘要翻译： 一种使用乘法器振荡产生随机数的方法，所述方法包括提供耦合以接收第一数字输入和第二数字输入的乘法器电路，其中所述第一数字输入和所述第二数字输入是异步信号和所述第一数字输入 包括基于所述乘法器电路的输出的反馈信号; 允许乘数进入反馈振荡状态; 以及基于乘法器电路的输出产生随机数。 该方法还可以包括提供接收反馈信号的多个加法器。
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4.发明授权Error checking parity and syndrome of a block of data with relocated parity bits 有权错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验公开(公告)号：US07895509B1
公开(公告)日：2011-02-22
申请号：US12188935
申请日：2008-08-08
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译： 描述了用于错误检查信息的方法和装置。 配置数据包括数据位和奇偶校验位。 值得注意的是，可以重新定位奇偶校验位以确定校正子值。 通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。 识别配置数据的每个单词的位置。 确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。 存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。
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5.发明授权Programmable integrated circuit with selective programming to compensate for process variations and/or mask revisions 有权具有选择性编程的可编程集成电路，以补偿过程变化和/或掩模修订公开(公告)号：US07368940B1
公开(公告)日：2008-05-06
申请号：US11449240
申请日：2006-06-08
申请人： David P. Schultz
发明人： David P. Schultz
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17764 , H03K19/17768 , H03K19/1778
摘要： Programmable integrated circuits (ICs) that compensate for process variations and/or mask revisions in a programmable integrated circuit (IC). An exemplary IC includes two programming ports, two programmable circuits (e.g., digital and analog), a non-volatile memory, and a configuration control circuit coupled to the programmable circuits and non-volatile memory. In some embodiments, one port can be used for storing data in the non-volatile memory, while the other port can be used for providing a configuration bitstream to the configuration control circuit. The non-volatile memory can be used to store a value that identifies a process corner and/or mask revision for the programmable IC. The configuration control circuit monitors data arriving in the configuration bitstream, and selectively either ignores the data or uses the data to configure the IC (e.g., the analog circuit), based on a comparison of a code key in the bitstream with the value stored in the non-volatile memory.
摘要翻译： 可编程集成电路（IC），可补偿可编程集成电路（IC）中的工艺变化和/或掩模修订。 示例性IC包括两个编程端口，两个可编程电路（例如数字和模拟），非易失性存储器以及耦合到可编程电路和非易失性存储器的配置控制电路。 在一些实施例中，一个端口可用于将数据存储在非易失性存储器中，而另一个端口可用于向配置控制电路提供配置比特流。 非易失性存储器可用于存储识别可编程IC的过程转角和/或掩模版本的值。 配置控制电路监视到达配置比特流中的数据，并且基于比特流中的代码密钥与存储在比特流中的值进行比较来选择性地忽略数据或使用数据来配置IC（例如，模拟电路） 非易失性存储器。
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公开(公告)号：US07314174B1
公开(公告)日：2008-01-01
申请号：US10970964
申请日：2004-10-22
CPC分类号： H03K19/177
摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.
摘要翻译： 一种用于在集成电路中编程配置存储单元的系统。 该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。
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7.发明授权Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability 有权具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案公开(公告)号：US07142442B1
公开(公告)日：2006-11-28
申请号：US10796750
申请日：2004-03-08
CPC分类号： G11C29/50 , G11C7/12 , G11C11/41 , G11C11/419 , G11C2029/1204
摘要： A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.
摘要翻译： 存储器包括多个行段，其中每个行段具有耦合到对应的数据段段对的多个存储器单元。 数据线驱动器电路提供在行段之间以缓冲相邻数据段上的信号。 控制电路耦合到至少一个行段，并且向至少一个行段和数据线驱动器电路提供控制信号。
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公开(公告)号：US6034557A
公开(公告)日：2000-03-07
申请号：US127309
申请日：1998-07-31
申请人： David P. Schultz , Scott O. Frake
发明人： David P. Schultz , Scott O. Frake
CPC分类号： H03K5/133 , H03K2005/0013 , H03K2005/00143 , H03K2005/00202
摘要： Described are delay circuits that are relatively insensitive to changes in temperature and supply voltage. A delay circuit includes at least one inverter circuit made up of a pair of transistors. The inverter responds to voltage changes on the input terminal by providing corresponding inverse changes on the output terminal. The speed at which the inverter responds to voltage changes on the input terminal depends upon the ability of one or both transistors to conduct current to or from the output terminal. The ability of one or both transistors in the inverter to move charge to or from the output terminal is restricted to reduce the switching speed of the inverter, thus imposing a delay on the input signal. Further, the restricted current is provided at a reference level that is relatively insensitive to temperature changes and supply-voltage fluctuations.
摘要翻译： 描述了对温度和电源电压变化相对不敏感的延迟电路。 延迟电路包括由一对晶体管构成的至少一个反相器电路。 变频器通过在输出端子上提供相应的反向变化来响应输入端子上的电压变化。 变频器响应输入端子上的电压变化的速度取决于一个或两个晶体管对输出端子传导电流的能力。 逆变器中的一个或两个晶体管向输出端子或从输出端子移动电荷的能力受到限制，以降低逆变器的开关速度，从而对输入信号施加延迟。 此外，限制电流被提供在对温度变化和电源 - 电压波动相对不敏感的参考电平。
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9.发明授权Method and apparatus for obtaining and using antifuse testing information to increase programmable device yield 失效用于获得和使用反熔丝测试信息以增加可编程器件产量的方法和装置
公开(公告)号：US5815404A
公开(公告)日：1998-09-29
申请号：US543531
申请日：1995-10-16
IPC分类号： G01R31/3185 , G06F11/00 , G06F11/20 , G06F11/22 , G11C29/44 , G01R31/07 , G06F17/18 , G11C29/00
CPC分类号： G11C29/44 , G01R31/318516 , G06F11/2205
摘要： A method and apparatus for creating and utilizing a database of defective antifuses on a programmable logic device and comparing the list to a catalog of required connections in a design, wherein the process of comparing the two lists will determine whether the device, although flawed, is nonetheless compatible with the design to be implemented, thereby increasing device yield.
摘要翻译： 一种用于在可编程逻辑器件上创建和利用有缺陷反熔丝的数据库并将该列表与设计中的所需连接的目录进行比较的方法和装置，其中比较两个列表的过程将确定该装置虽然有缺陷， 尽管与要实现的设计兼容，从而提高了设备产量。
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公开(公告)号：US5694047A
公开(公告)日：1997-12-02
申请号：US512795
申请日：1995-08-09
CPC分类号： G01R31/318519 , G01R27/205 , G11C17/18 , G01R27/14
摘要： A method and system for measuring programmed antifuse resistance in an FPGA without disturbing the antifuse resistance. The method includes estimating a plurality of subparts of the programming path connecting low and high programming voltage sources on the FPGA device, measuring the path as a whole, and subtracting the sum total of the subparts from the whole path measurement, thereby deriving the antifuse resistance. If the derived antifuse resistance is higher than desired, programming and measurement may be repeated to ensure device longevity and accurate timing for implemented designs.
摘要翻译： 用于测量FPGA中编程反熔丝电阻的方法和系统，而不会干扰反熔丝电阻。 该方法包括估计连接FPGA器件上的低编程电压源和高编程电压源的编程路径的多个子部分，测量整个路径，并从整个路径测量中减去子部分的总和，从而导出反熔丝电阻 。 如果得到的反熔丝电阻高于期望值，则可以重复编程和测量，以确保器件寿命和实施设计的精确时序。
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