公开(公告)号：US07051177B2

公开(公告)日：2006-05-23

申请号：US10210359

申请日：2002-07-31

申请人： Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Toshihiko Kurihara ,  Michitaka Okuno ,  Masahiro Tokoro

发明人： Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Toshihiko Kurihara ,  Michitaka Okuno ,  Masahiro Tokoro

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F11/3466 ,  G06F11/3419 ,  G06F12/0897 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： A method for determining the latency for a particular level of memory within a hierarchical memory system is disclosed. A performance monitor counter is allocated to count the number of loads (load counter) and for counting the number of cycles (cycle counter). The method begins with a processor determining which load to select for measurement. In response to the determination, the cycle counter value is stored in a rewind register. The processor issues the load and begins counting cycles. In response to the load completing, the level of memory for the load is determined. If the load was executed from the desired memory level, the load counter is incremented. Otherwise, the cycle counter is rewound to its previous value.

摘要翻译： 公开了一种用于确定分层存储器系统内特定级别的存储器的等待时间的方法。 分配性能监视计数器来计数负载数（负载计数器）和计数周期数（循环计数器）。 该方法开始于处理器确定要选择用于测量的负载。 响应于该确定，周期计数器值被存储在倒带寄存器中。 处理器发出负载并开始计数周期。 响应于负载完成，确定负载的存储器级别。 如果从期望的存储器级别执行负载，则负载计数器递增。 否则，循环计数器将重绕到其先前的值。

公开(公告)号：US07047398B2

公开(公告)日：2006-05-16

申请号：US10210358

申请日：2002-07-31

申请人： Toshihiko Kurihara ,  Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Michitaka Okuno ,  Masahiro Tokoro

发明人： Toshihiko Kurihara ,  Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Michitaka Okuno ,  Masahiro Tokoro

IPC分类号： G06F11/34

CPC分类号： G06F11/348 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  G06F11/3466 ,  G06F2201/88

摘要： A method and system for identifying instruction completion delays for a group of instructions in a computer processor. Each instruction in the group of instructions has a status indicator that identifies what is preventing that instruction from completing execution. Examples of completion delays are cache misses, data dependencies or simply the time required for an execution unit in the computer processor to process the instruction. As each instruction finishes executing, its associated status indicator is cleared to indicate that the instruction is no longer waiting to execute. The last instruction to execute is the instruction that is holding up completion of the entire group, and thus the cause for the completion delay of the last instruction is recorded as the cause of completion delay for the entire group.

摘要翻译： 一种用于识别计算机处理器中的一组指令的指令完成延迟的方法和系统。 指令组中的每个指令都有一个状态指示器，用于标识阻止该指令完成执行的内容。 完成延迟的示例是缓存未命中，数据依赖性或简单地计算机处理器中的执行单元处理指令所需的时间。 每个指令执行完毕后，相关状态指示灯将被清除，表示该指令不再等待执行。 执行的最后一条指令是保持整个组的完成的指令，因此将最后指令的完成延迟的原因记录为整个组的完成延迟的原因。

公开(公告)号：US06910120B2

公开(公告)日：2005-06-21

申请号：US10210357

申请日：2002-07-31

申请人： Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Toshihiko Kurihara ,  Michitaka Okuno ,  Masahiro Tokoro

发明人： Hung Qui Le ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Toshihiko Kurihara ,  Michitaka Okuno ,  Masahiro Tokoro

IPC分类号： G06F9/00 ,  G06F9/38 ,  G06F11/34

CPC分类号： G06F9/3842 ,  G06F9/3861

摘要： A circuit and method for maintaining a correct value in performance monitor counter within a speculative computer microprocessor is disclosed. In response to determining the begin of speculative execution within the microprocessor, the value of the performance monitor counter is stored in a rewind register. The performance monitor counter is incremented in response to predetermined events. If the microprocessor determines the speculative execution was incorrect, the value of the rewind register is loaded into the counter, restoring correct value for the counter.

摘要翻译： 公开了一种用于在推测性计算机微处理器内在性能监视计数器中维持正确值的电路和方法。 响应于确定微处理器内的推测执行开始，性能监视计数器的值被存储在倒带寄存器中。 性能监视计数器响应于预定事件递增。 如果微处理器确定推测执行不正确，倒带寄存器的值将被加载到计数器中，恢复计数器的正确值。

公开(公告)号：US06895399B2

公开(公告)日：2005-05-17

申请号：US09951959

申请日：2001-09-13

申请人： Alexander Erik Mericas

发明人： Alexander Erik Mericas

IPC分类号： G06F9/50 ,  G06F17/00

CPC分类号： G06F9/5011 ,  G06F2209/507

摘要： A data processing system, method, and product are disclosed for dynamically allocating resources for multiple, different types of events that occur within a microprocessor. Multiple, different unallocated resources are provided. One of these unallocated resources are allocated only in response to a first occurrence of an event that is one of the different types of events. Thus, resources remain unallocated until a first occurrence of events for which resources are then allocated.

摘要翻译： 公开了一种数据处理系统，方法和产品，用于为在微处理器内发生的多种不同类型的事件动态分配资源。 提供了多种不同的未分配资源。 这些未分配资源中的一个仅在响应于作为不同类型的事件之一的事件的第一次出现时被分配。 因此，资源保持未分配，直到首先发生资源然后被分配的事件。

公开(公告)号：US06718403B2

公开(公告)日：2004-04-06

申请号：US09734116

申请日：2000-12-11

申请人： Joel Roger Davidson ,  Judith E. K. Laurens ,  Alexander Erik Mericas

发明人： Joel Roger Davidson ,  Judith E. K. Laurens ,  Alexander Erik Mericas

IPC分类号： G06E300

CPC分类号： G06F13/4217 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： A microprocessor including a performance monitor unit is disclosed. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus. Whereas the performance monitor unit is typically capable of monitoring the direct event signals in any of its counters, the indirect event signals may be selectively routed to the counters. The shared bus may be divided into sub-groups or byte lanes where the byte lanes are selectively routed to the set of performance monitor counters. The state of a control register may determine the event that is monitored in the corresponding counter. In one embodiment, the control register provides a set of signals that are connected to the select inputs of one or more multiplexers. The multiplexers receive multiple events signals and, based on the state of their select signals, route one of the received event signals to the corresponding performance monitor counter. Specified states of the select signals may result in the disabling of the corresponding counter or enabling the counter to count system clock cycles rather than any performance event.

摘要翻译： 公开了一种包括性能监视器单元的微处理器。 性能监视器单元包括一组性能监视计数器和一组相应的控制电路和可编程控制寄存器。 性能监视器单元从处理器的功能单元接收第一组事件信号。 第一组事件中的每一个直接从适当的功能单元路由到性能监视器单元。 性能监视器单元进一步接收至少第二组事件信号。 在一个实施例中，经由处理器的性能监视总线接收第二组事件信号。 性能监视器总线通常是可以从处理器的任何功能单元接收信号的共享总线。 功能单元可以包括复用电路，其确定哪个功能单元具有共享总线的掌握。 而性能监视器单元通常能够监视任何其计数器中的直接事件信号，间接事件信号可被选择性地路由到计数器。 共享总线可以被划分成子组或字节通道，其中字节通道被选择性地路由到一组性能监视计数器。 控制寄存器的状态可以确定在相应计数器中监视的事件。 在一个实施例中，控制寄存器提供连接到一个或多个多路复用器的选择输入的一组信号。 多路复用器接收多个事件信号，并且基于其选择信号的状态，将接收的事件信号中的一个路由到相应的性能监视计数器。 选择信号的指定状态可能导致禁用相应的计数器或使计数器能够对系统时钟周期进行计数，而不是任何性能事件。

公开(公告)号：US06415378B1

公开(公告)日：2002-07-02

申请号：US09343359

申请日：1999-06-30

申请人： Joel Roger Davidson ,  Judith K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick ,  Joel M. Tendler

发明人： Joel Roger Davidson ,  Judith K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick ,  Joel M. Tendler

IPC分类号： G06F1100

CPC分类号： G06F11/3466

摘要： A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

摘要翻译： 提供了一种用于调试指令管线内的指令执行的方法和系统。 数据处理系统中的处理器包含指令流水线单元。 指令可以被标记，并且响应于指令流水线单元完成其对带标签的指令的处理，声明级完成信号。 流水线处理器外部的执行监视器在执行标记指令期间监视阶段完成信号。 执行监视器可以是在执行监视器的显示装置上实时显示级完成信号的逻辑分析器。 可以基于诸如指令的地址的指令选择规则来选择要被标记的指令。

公开(公告)号：US07711994B2

公开(公告)日：2010-05-04

申请号：US12131070

申请日：2008-05-31

申请人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

发明人： Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella

IPC分类号： G06F11/00

CPC分类号： G06F11/00

摘要： An apparatus, system and method of integrating performance monitor data with thermal event information are provided. A thermal event, in this case, is when the temperature of a chip within which is embedded a processor exceeds a user-configurable value while the processor is processing instructions and/or using storage devices that are being monitored. In any event, when the thermal event occurs, the temperature of the chip along with the performance monitor data is stored for future uses, which include performance and diagnostic analyses.

摘要翻译： 提供了一种将性能监控数据与热事件信息集成的设备，系统和方法。 在这种情况下，当事件处理器处理指令和/或使用正被监视的存储设备时，嵌入处理器的芯片的温度超过用户可配置值时，就会发生热事件。 无论如何，当发生热事件时，将存储芯片的温度以及性能监视数据以供将来使用，包括性能和诊断分析。

公开(公告)号：US07620801B2

公开(公告)日：2009-11-17

申请号：US11055848

申请日：2005-02-11

申请人： James Wilson Bishop ,  Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Dung Quoc Nguyen ,  Philip Lee Vitale

发明人： James Wilson Bishop ,  Michael Stephen Floyd ,  Alexander Erik Mericas ,  Robert Dominick Mirabella ,  Dung Quoc Nguyen ,  Philip Lee Vitale

IPC分类号： G06F9/30

CPC分类号： G06F11/3409 ,  G06F11/3466 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： A method for pseudo-randomly, without bias, selecting instructions for marking in a microprocessor. Responsive to reading an instruction from an instruction cache, an instruction tag associated with the instruction is compared against a pseudo-randomly generated value in a linear feedback shift register (LFSR). If the instruction tag matches the value in the LFSR, a mark bit, indicating the instruction is a marked instruction, is sent with the instruction to an execution unit. Responsive to an indication from the performance monitor, the value in the LFSR is incremented prior to selecting a next instruction to mark. If the value equals a predetermined prime number of increments, the value is reset to all ones to avoid any harmonics with the code stream being executed. Upon receiving the marked instruction, the execution unit combines the marked bit with a selected event and reports the marked event to the performance monitor.

摘要翻译： 一种用于伪随机，无偏差的方法，用于在微处理器中选择用于标记的指令。 响应于从指令高速缓存读取指令，将与指令相关联的指令标记与线性反馈移位寄存器（LFSR）中的伪随机生成值进行比较。 如果指令标签与LFSR中的值相匹配，则表示指令是标记指令的标记位与指令一起发送到执行单元。 响应于性能监视器的指示，LFSR中的值在选择下一个要标记的指令之前递增。 如果该值等于预定的素数增量，则该值被重置为全部值，以避免与正在执行的码流的任何谐波。 在接收到标记指令之后，执行单元将所标记的位与所选择的事件相结合，并将标记的事件报告给性能监视器。

公开(公告)号：US20090031173A1

公开(公告)日：2009-01-29

申请号：US12206967

申请日：2008-09-09

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/2268 ,  G06F11/3476 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

摘要翻译： 在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。 处理器包含在数据处理系统中。 处理器包括使用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 确定存储跟踪数据所需的特定大小的系统存储器。 硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。 固件选择系统内存中的特定位置。 所有特定位置在一起是特定的尺寸。 固件分配由硬件跟踪设备专门使用的特定位置。

公开(公告)号：US07437617B2

公开(公告)日：2008-10-14

申请号：US11055845

申请日：2005-02-11

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

摘要翻译： 公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。