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    Determining soft data for combinations of memory cells
    34.
    发明授权
    Determining soft data for combinations of memory cells 有权
    确定存储单元组合的软数据

    公开(公告)号：US08737139B2

    公开(公告)日：2014-05-27

    申请号：US13444443

    申请日：2012-04-11

    申请人： Violante Moschiano ,  Tommaso Vali ,  Mark A. Hawes

    发明人： Violante Moschiano ,  Tommaso Vali ,  Mark A. Hawes

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

    摘要： The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.

    摘要翻译： 本公开包括用于确定存储器单元的组合的软数据的装置和方法。 多个实施例包括存储单元的阵列，其包括第一和第二存储单元，每个第一和第二存储器单元可编程为多个程序状态之一，其中第一和第二存储器单元的编程状态的组合对应于多个 数据状态，以及耦合到阵列并被配置为确定与第一和第二存储器单元的程序状态相关联的软数据的缓冲器和/或控制器以及与对应于程序状态的组合的数据状态相关联的软数据 至少部分地基于与第一和第二存储器单元的程序状态相关联的软数据。

    Sense amplifier for a non-volatile memory device
    37.
    发明授权
    Sense amplifier for a non-volatile memory device 有权
    用于非易失性存储器件的感应放大器

    公开(公告)号：US07394699B2

    公开(公告)日：2008-07-01

    申请号：US11651687

    申请日：2007-01-10

    申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    IPC分类号： G11C16/06

    CPC分类号： G11C16/26

    摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.

    摘要翻译： 存储器件具有多个存储单元，每个存储器单元都耦合到位线。 反馈晶体管耦合到位线，并对位线的预充电状态提供电压反馈。 偏置晶体管耦合到反馈晶体管。 偏置晶体管响应于偏置晶体管上的参考电压向反馈晶体管提供偏置电压。 共源共栅连接的晶体管耦合到反馈晶体管和偏置晶体管。 该晶体管向偏置晶体管提供稳定的偏置电压。 输出锁存电路耦合到位线以提供存储器单元数据的锁存输出。

    Sense amplifier for a non-volatile memory device
    38.
    发明申请
    Sense amplifier for a non-volatile memory device 有权

    公开(公告)号：US20070115742A1

    公开(公告)日：2007-05-24

    申请号：US11651687

    申请日：2007-01-10

    申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    IPC分类号： G11C7/00

    CPC分类号： G11C16/26

    摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.

    Sense amplifier for a non-volatile memory device
    39.
    发明授权
    Sense amplifier for a non-volatile memory device 有权
    用于非易失性存储器件的感应放大器

    公开(公告)号：US07173856B2

    公开(公告)日：2007-02-06

    申请号：US10912520

    申请日：2004-08-05

    申请人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    发明人： Tommaso Vali ,  Giovanni Santin ,  Michele Incarnati

    IPC分类号： G11C16/06 ,  G11C7/02

    CPC分类号： G11C7/12 ,  G11C7/067 ,  G11C7/18 ,  G11C16/24 ,  G11C16/26

    摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.

    摘要翻译： 存储器件具有多个存储单元，每个存储器单元都耦合到位线。 反馈晶体管耦合到位线，并对位线的预充电状态提供电压反馈。 偏置晶体管耦合到反馈晶体管。 偏置晶体管响应于偏置晶体管上的参考电压向反馈晶体管提供偏置电压。 共源共栅连接的晶体管耦合到反馈晶体管和偏置晶体管。 该晶体管向偏置晶体管提供稳定的偏置电压。 输出锁存电路耦合到位线以提供存储器单元数据的锁存输出。

    Selective slow programming convergence in a flash memory device
    40.
    发明申请
    Selective slow programming convergence in a flash memory device 有权
    闪存设备中选择性慢编程收敛

    公开(公告)号：US20060285392A1

    公开(公告)日：2006-12-21

    申请号：US11414982

    申请日：2006-05-01

    申请人： Michele Incarnati ,  Giovanni Santin ,  Tommaso Vali

    发明人： Michele Incarnati ,  Giovanni Santin ,  Tommaso Vali

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3404

    摘要： A plurality of memory cells are programmed with incrementally increased programming pulses applied to word lines to which the memory cells are coupled. After each pulse, a verify operation determines the threshold voltage for each cell. When the threshold voltage reaches a pre-verify threshold, only the bit line connected to that particular cell is biased with an intermediate voltage that slows down the change in the Vt of the cell. The other cells continue to be programmed at their normal pace. As the Vt for each cell reaches the pre-verify level, it is biased with the intermediate voltage. All of the bit lines are biased with an inhibit voltage as their threshold voltages reach the verify voltage threshold.

    摘要翻译： 多个存储器单元被编程，其中增加的编程脉冲被施加到存储器单元耦合到的字线。 在每个脉冲之后，验证操作确定每个单元的阈值电压。 当阈值电压达到预验证阈值时，只有连接到该特定单元的位线被中间电压偏置，该中间电压降低了单元的Vcc变化。 其他细胞继续按其正常速度进行编程。 由于每个单元的V OUT达到预验证电平，所以它被中间电压偏置。 当它们的阈值电压达到验证电压阈值时，所有位线都被抑制电压偏置。