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    Storing operational information in an array of memory cells
    5.
    发明授权
    Storing operational information in an array of memory cells 有权
    将操作信息存储在存储单元阵列中

    公开(公告)号：US08437217B2

    公开(公告)日：2013-05-07

    申请号：US13012020

    申请日：2011-01-24

    申请人： Theodore T. Pekny

    发明人： Theodore T. Pekny

    IPC分类号： G11C8/00

    CPC分类号： G11C29/789 ,  G11C2029/4402 ,  G11C2229/723

    摘要： The present disclosure includes methods, devices, modules, and systems for storing operational information in an array of memory cells. One method embodiment includes storing data units of operational information in memory cells of at least one row of a first block of memory cells. The method also includes using a column scramble to shift the order of the data units. The method includes storing the data units in memory cells of at least one row of a second block of memory cells, wherein an order of the data units stored in the at least one row of the second block is different than an order of the data units stored in memory cells of the at least one row of the first block.

    摘要翻译： 本公开包括用于将操作信息存储在存储器单元阵列中的方法，设备，模块和系统。 一种方法实施例包括将操作信息的数据单元存储在存储器单元的第一块的至少一行的存储单元中。 该方法还包括使用列加扰来移动数据单元的顺序。 该方法包括将数据单元存储在存储器单元的第二块的至少一行的存储器单元中，其中存储在第二块的至少一行中的数据单元的顺序不同于数据单元的顺序 存储在第一块的至少一行的存储单元中。

    Methods of forming a memory array with a pair of memory-cell strings to a single conductive pillar
    6.
    发明授权
    Methods of forming a memory array with a pair of memory-cell strings to a single conductive pillar 有权
    将一对存储单元串形成存储器阵列到单个导电柱的方法

    公开(公告)号：US08329513B2

    公开(公告)日：2012-12-11

    申请号：US13047215

    申请日：2011-03-14

    申请人： Theodore T. Pekny

    发明人： Theodore T. Pekny

    IPC分类号： H01L21/82

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/0649

    摘要： A method of forming a memory array includes forming first and second strings of serially-coupled memory cells respectively on first and second sides of a conductive pillar. Forming the first string of memory cells includes forming a first control gate on the first side of the conductive pillar and interposing a first charge trap between the first side of the conductive pillar and the first control gate. Forming the second string of memory cells comprises forming a second control gate on the second side of the conductive pillar and interposing a second charge trap between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other, and the first and second control gates are electrically isolated from each other.

    摘要翻译： 形成存储器阵列的方法包括分别在导电柱的第一和第二侧上形成串联耦合的存储器单元的第一和第二串。 形成第一串存储单元包括在导电柱的第一侧上形成第一控制栅极，并且在导电柱的第一侧和第一控制栅极之间插入第一电荷陷阱。 形成第二串存储单元包括在导电柱的第二侧上形成第二控制栅极，并且在导电柱的第二侧和第二控制栅极之间插入第二电荷陷阱。 第一和第二充电陷阱彼此电隔离，并且第一和第二控制栅极彼此电隔离。

    Multi-partition memory with separated read and algorithm datalines
    7.
    发明授权
    Multi-partition memory with separated read and algorithm datalines 有权
    具有分离的读取和算法数据的多分区存储器

    公开(公告)号：US08233322B2

    公开(公告)日：2012-07-31

    申请号：US10683075

    申请日：2003-10-10

    申请人： Theodore T. Pekny ,  Stephen J. Gualandri

    发明人： Theodore T. Pekny ,  Stephen J. Gualandri

    IPC分类号： G11C16/04

    CPC分类号： G11C5/025 ,  G11C7/18 ,  G11C16/26

    摘要： A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and blockout of multiple operations in a single block of the memory.

    摘要翻译： 用于并发操作的多分区存储器和架构通过为多个分区提供公共读取读出放大器和程序路径来减少电路开销。 用于读取和算法操作的长单独数据允许在单个存储器块中并行操作和阻止多个操作。

    METHODS OF FORMING A MEMORY ARRAY WITH A PAIR OF MEMORY-CELL STRINGS TO A SINGLE CONDUCTIVE PILLAR
    8.
    发明申请
    METHODS OF FORMING A MEMORY ARRAY WITH A PAIR OF MEMORY-CELL STRINGS TO A SINGLE CONDUCTIVE PILLAR 有权
    形成记忆体阵列与存储单元对相对单个导电柱的方法

    公开(公告)号：US20110159645A1

    公开(公告)日：2011-06-30

    申请号：US13047215

    申请日：2011-03-14

    申请人： Theodore T. Pekny

    发明人： Theodore T. Pekny

    IPC分类号： H01L21/8239

    CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/0649

    摘要： A method of forming a memory array includes forming first and second strings of serially-coupled memory cells respectively on first and second sides of a conductive pillar. Forming the first string of memory cells includes forming a first control gate on the first side of the conductive pillar and interposing a first charge trap between the first side of the conductive pillar and the first control gate. Forming the second string of memory cells comprises forming a second control gate on the second side of the conductive pillar and interposing a second charge trap between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other, and the first and second control gates are electrically isolated from each other.

    摘要翻译： 形成存储器阵列的方法包括分别在导电柱的第一和第二侧上形成串联耦合的存储器单元的第一和第二串。 形成第一串存储单元包括在导电柱的第一侧上形成第一控制栅极，并且在导电柱的第一侧和第一控制栅极之间插入第一电荷陷阱。 形成第二串存储单元包括在导电柱的第二侧上形成第二控制栅极，并且在导电柱的第二侧和第二控制栅极之间插入第二电荷陷阱。 第一和第二充电陷阱彼此电隔离，并且第一和第二控制栅极彼此电隔离。

    Test mode for multi-chip integrated circuit packages
    9.
    发明授权
    Test mode for multi-chip integrated circuit packages 有权
    多芯片集成电路封装的测试模式

    公开(公告)号：US07802157B2

    公开(公告)日：2010-09-21

    申请号：US11472618

    申请日：2006-06-22

    申请人： Theodore T. Pekny

    发明人： Theodore T. Pekny

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31701 ,  G01R31/31722 ,  G01R31/31723

    摘要： When a test mode of a controller of a multi-chip integrated circuit package is activated, external signal lines coupled to the controller are re-mapped to signal lines of one of the integrated circuit devices of the multi-chip integrated circuit package to permit direct testing of the integrated circuit device.

    摘要翻译： 当激活多芯片集成电路封装的控制器的测试模式时，耦合到控制器的外部信号线被重新映射到多芯片集成电路封装的集成电路器件之一的信号线，以允许直接 测试集成电路设备。

    SYSTEM AND METHOD FOR SETTING ACCESS AND MODIFICATION FOR SYNCHRONOUS SERIAL INTERFACE NAND
    10.
    发明申请
    SYSTEM AND METHOD FOR SETTING ACCESS AND MODIFICATION FOR SYNCHRONOUS SERIAL INTERFACE NAND 有权
    用于同步串行接口NAND的设置访问和修改的系统和方法

    公开(公告)号：US20090103362A1

    公开(公告)日：2009-04-23

    申请号：US11873826

    申请日：2007-10-17

    申请人： Theodore T. Pekny ,  Victor Y. Tsai

    发明人： Theodore T. Pekny ,  Victor Y. Tsai

    IPC分类号： G11C8/18 ,  G11C16/06

    CPC分类号： G11C7/1021 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/145 ,  G06F13/1694 ,  G06F2212/1052 ,  G11C7/1072

    摘要： The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.

    摘要翻译： 本发明包括使用从主机到NAND闪存器件的串行外设接口（SPI）通信来修改NAND闪存器件的设置的系统和方法。 一个实施例通常包括将启用信号发送到第一存储器电路输入，向第二存储器电路输入发送时钟信号，向第三存储器电路输入发送与时钟信号同步的命令信号，发送与第一存储器电路输入同步的存储器寄存器地址信号 时钟信号输入到第三存储器电路，并将与时钟信号同步的设置信号发送到第三存储器电路输入。