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    ELECTRICAL FUSE STRUCTURE FOR HIGHER POST-PROGRAMMING RESISTANCE
    32.
    发明申请
    ELECTRICAL FUSE STRUCTURE FOR HIGHER POST-PROGRAMMING RESISTANCE 失效
    用于更高后编程电阻的电熔丝结构

    公开(公告)号：US20080217733A1

    公开(公告)日：2008-09-11

    申请号：US11683071

    申请日：2007-03-07

    申请人： Subramanian S. Iyer ,  Deok-Kee Kim ,  Chandrasekara Kothandaraman ,  Byeongju Park

    发明人： Subramanian S. Iyer ,  Deok-Kee Kim ,  Chandrasekara Kothandaraman ,  Byeongju Park

    IPC分类号： H01L23/58

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides an electrical fuse structure for achieving a post-programming resistance distribution with higher resistance values and to enhance the reliability of electrical fuse programming. A partly doped electrical fuse structure with undoped semiconductor material in the cathode combined with P-doped semiconductor material in the fuselink and anode is disclosed and the data supporting the superior performance of the disclosed electrical fuse is shown.

    摘要翻译： 本发明提供一种用于实现具有更高电阻值的后编程电阻分布并提高电熔丝编程的可靠性的电熔丝结构。 公开了在阴极中与掺杂了P掺杂的半导体材料结合在阴极中的未掺杂半导体材料的部分掺杂的电熔丝结构，并且示出了所公开的电熔丝的优异性能的数据。

    POST STI TRENCH CAPACITOR
    33.
    发明申请
    POST STI TRENCH CAPACITOR 失效
    POST STI TRENCH电容器

    公开(公告)号：US20080173977A1

    公开(公告)日：2008-07-24

    申请号：US11624385

    申请日：2007-01-18

    申请人： Anil K. Chinthakindi ,  Deok-Kee Kim ,  Xi Li

    发明人： Anil K. Chinthakindi ,  Deok-Kee Kim ,  Xi Li

    IPC分类号： H01L21/02 ,  H01L29/92

    CPC分类号： H01L29/94 ,  H01L27/0805 ,  H01L28/91 ,  H01L29/66181

    摘要： A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.

    摘要翻译： 在由诸如凹陷隔离或浅沟槽隔离的隔离结构限定的沟槽中形成具有用于去耦应用的适当大值的电容器。 电容器提供与有源区域共同延伸的接触区域，并且可以单独或少量可靠地形成。 板触点优选通过延伸到形成电容器板的掺杂剂扩散区域之间或之间的注入区域制成。 可以通过形成隔离结构之后的过程形成电容器，使得可以使用优选的软掩模工艺来形成隔离结构和工艺共同性，并避免兼容性约束，同时电容器形成过程可以与其他处理共同执行 结构。

    ELECTRICALLY PROGRAMMABLE FUSE WITH ASYMMETRIC STRUCTURE
    34.
    发明申请
    ELECTRICALLY PROGRAMMABLE FUSE WITH ASYMMETRIC STRUCTURE 审中-公开
    具有非对称结构的电气可编程保险丝

    公开(公告)号：US20070284693A1

    公开(公告)日：2007-12-13

    申请号：US11423181

    申请日：2006-06-09

    申请人： Deok-Kee Kim ,  Byeongju Park

    发明人： Deok-Kee Kim ,  Byeongju Park

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrically programmable fuse is provided which includes a cathode, an anode, and a fuse link conductively connecting the cathode to the anode. The cathode, the anode and the fuse link each have a length in a direction of current between the anode and cathode. Each of the cathode, the anode and the fuse link also has a width in a direction transverse to the respective length. At a cathode junction where the cathode meets the fuse link, the width of the fuse link decreases substantially and abruptly relative to the width of the cathode. The width of the fuse link increases only gradually in a direction towards an anode junction where the fuse link meets the anode.

    摘要翻译： 提供了电可编程保险丝，其包括阴极，阳极和将阴极导电连接到阳极的熔断体。 阴极，阳极和熔断体在阳极和阴极之间的电流方向上具有长度。 阴极，阳极和熔丝链中的每一个也在横向于相应长度的方向上具有宽度。 在阴极与熔丝连接的阴极结处，熔丝链的宽度相对于阴极的宽度基本上急剧下降。 熔丝链的宽度仅在熔丝链接到阳极的阳极结的方向上逐渐增加。

    Efuse containing sige stack
    37.
    发明授权
    Efuse containing sige stack 有权
    Efuse包含sige堆栈

    公开(公告)号：US08299570B2

    公开(公告)日：2012-10-30

    申请号：US13189016

    申请日：2011-07-22

    申请人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

    发明人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

    摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

    Structure and method to form dual silicide e-fuse
    38.
    发明授权
    Structure and method to form dual silicide e-fuse 有权
    双硅化物电熔丝的结构和方法

    公开(公告)号：US08013419B2

    公开(公告)日：2011-09-06

    申请号：US12136246

    申请日：2008-06-10

    申请人： Deok-Kee Kim ,  Ahmet S Ozcan ,  Haining S Yang

    发明人： Deok-Kee Kim ,  Ahmet S Ozcan ,  Haining S Yang

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link.

    摘要翻译： 电熔丝结构和方法具有阳极，熔丝链和阴极。 熔丝链的第一端连接到阳极，并且与第一端相对的熔丝连接的第二端连接到阴极。 该结构还包括阴极上的阳极和熔丝链上的第一硅化物层和不同于第一硅化物层的第二硅化物层。 第一硅化物层和第二硅化物层之间的差异在熔丝链的第二端引起增强的磁通发散区域。

    Dual stress STI
    39.
    发明授权
    Dual stress STI 有权
    双重应激STI

    公开(公告)号：US07927968B2

    公开(公告)日：2011-04-19

    申请号：US12125106

    申请日：2008-05-22

    申请人： Deok-Kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    发明人： Deok-Kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

    摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

    摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

    Electrical fuse having a fully silicided fuselink and enhanced flux divergence
    40.
    发明授权
    Electrical fuse having a fully silicided fuselink and enhanced flux divergence 有权
    电熔丝具有完全硅化的富熔体和增强的焊剂分散

    公开(公告)号：US07838963B2

    公开(公告)日：2010-11-23

    申请号：US11925164

    申请日：2007-10-26

    申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

    发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

    IPC分类号： H01L29/86

    CPC分类号： H01L23/5256 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

    摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。