公开(公告)号：US07923806B2

公开(公告)日：2011-04-12

申请号：US11084014

申请日：2005-03-21

申请人： Kenichi Watanabe

发明人： Kenichi Watanabe

IPC分类号： H01L29/00

CPC分类号： H01L21/76877 ,  H01L21/76805 ,  H01L21/76847 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device capable of restricting a void growth in a copper wiring. The semiconductor device comprises a semiconductor substrate, an insulation layer formed above the semiconductor substrate, a barrier metal layer that is a first damascene wiring buried in the insulation layer, defines the bottom face and the side faces, and also defines a first hollow part at the inner side, a copper wiring layer disposed in the first hollow part and defining a second hollow part at the inner side, a first damascene wiring disposed in the second hollow part and containing an auxiliary barrier metal layer separated from the barrier metal layer, and an insulating copper diffusion preventing film disposed on the first damascene wiring and the insulation layer.

摘要翻译： 一种能够限制铜布线中的空隙生长的半导体器件。 半导体器件包括半导体衬底，形成在半导体衬底上的绝缘层，作为掩埋在绝缘层中的第一镶嵌布线的阻挡金属层，限定底面和侧面，并且还限定第一中空部分 内侧，设置在第一中空部分中并在内侧限定第二中空部分的铜布线层，设置在第二中空部分中并且包含与阻挡金属层分离的辅助阻挡金属层的第一镶嵌布线，以及 设置在第一镶嵌布线和绝缘层上的绝缘铜扩散防止膜。

公开(公告)号：US20100289283A1

公开(公告)日：2010-11-18

申请号：US12445689

申请日：2007-10-12

申请人： Kenichi Watanabe ,  Takeshi Segawa ,  Hironobu Fujimoto

发明人： Kenichi Watanabe ,  Takeshi Segawa ,  Hironobu Fujimoto

IPC分类号： B25J15/06 ,  H01L21/683

CPC分类号： H01L21/67132 ,  H01L21/6838

摘要： A method is provided for picking up a chip 13 from a fixing jig 3 to which the chip 13 is fixed. The fixing jig 3 consists of a jig base 30 having a plurality of protrusions 36 on one side and a sidewall 35 having a height almost equivalent to that of the protrusion 36 at the outer circumference of the one side, and an contact layer 31 that is laminated on the surface of the jig base 30 having the protrusions 36 and that is bonded on the upper surface of the sidewall 35. A section space 37 is formed on the surface of the jig base 30 having the protrusions by the contact layer 31, the protrusions 36 and the sidewall 35, and at least one through hole 38 penetrating the outside and the section space 37 is provided in the jig base 30. The pickup method comprises the steps of fixing a chip, deforming the contact layer 31 by suctioning of air in the section space 37 through the through hole 38, and picking up the chip 13 completely from the contact layer 31 by suctioning the chip 13 from the upper surface side of the chip 13 by means of a suction collet 70.

摘要翻译： 提供了一种用于从固定夹具3拾取芯片13的方法，固定夹具3固定芯片13。 固定夹具3由在一侧具有多个突起36的夹具基座30和具有与一侧的外周的突起36的高度几乎相同的高度的侧壁35以及接触层31 层压在具有突起36的夹具基座30的表面上并且接合在侧壁35的上表面上。在具有突起的夹具基座30的表面上通过接触层31形成截面空间37， 突起36和侧壁35以及贯穿外部的至少一个通孔38，并且在夹具基座30中设置有截面空间37.拾取方法包括如下步骤：固定芯片，通过抽吸空气使接触层31变形 在截面空间37中通过通孔38，并且通过吸力夹头70从芯片13的上表面侧抽吸芯片13，完全从接触层31拾取芯片13。

公开(公告)号：US20100219508A1

公开(公告)日：2010-09-02

申请号：US12702729

申请日：2010-02-09

申请人： Kenichi Watanabe

发明人： Kenichi Watanabe

IPC分类号： H01L23/58 ,  G03F7/20

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate on which an internal circuit is formed in a central position an insulating layer formed over the semiconductor substrate, and a moisture-resistant ring formed by a metal plug embedded in the insulating layer, the moisture-resistant ring surrounding the internal circuit, the moisture-resistant ring extending over the semiconductor substrate in a shape, the moisture-resistant ring including a first extending portion linearly extending in a first direction in parallel to the surface of the semiconductor substrate, a vertical portion connected to the first extending portion extending in a second direction orthogonal to the first extending portion, and a second extending portion orthogonal to the vertical portion and parallel to the surface of the semiconductor substrate, the second extending portion spaced apart from the first extending portion, the second extending portion crossing the vertical portion.

摘要翻译： 半导体器件包括半导体衬底，其中在内部电路在中心位置形成在半导体衬底上形成的绝缘层，以及由嵌入绝缘层中的金属插塞形成的防潮环，围绕 所述内部电路，所述防湿环形成为在所述半导体基板上延伸的形状，所述防湿环包括与所述半导体基板的表面平行的第一方向上直线延伸的第一延伸部， 第一延伸部分，其在与第一延伸部分正交的第二方向上延伸;以及第二延伸部分，其垂直于垂直部分并平行于半导体基板的表面，第二延伸部分与第一延伸部分间隔开，第二延伸部分 横穿垂直部分的部分。

公开(公告)号：US07662985B2

公开(公告)日：2010-02-16

申请号：US12318736

申请日：2009-01-07

申请人： Mikio Yamahiro ,  Hisao Oikawa ,  Kenya Ito ,  Yasuhiro Yamamoto ,  Masami Tanaka ,  Nobumasa Ootake ,  Kenichi Watanabe ,  Kohji Ohno ,  Yoshinobu Tsujii ,  Takeshi Fukuda

发明人： Mikio Yamahiro ,  Hisao Oikawa ,  Kenya Ito ,  Yasuhiro Yamamoto ,  Masami Tanaka ,  Nobumasa Ootake ,  Kenichi Watanabe ,  Kohji Ohno ,  Yoshinobu Tsujii ,  Takeshi Fukuda

IPC分类号： C07F7/04

CPC分类号： C08G77/04 ,  C07F7/21 ,  C08F10/00 ,  C08F30/08 ,  C08F2500/03

摘要： A production process for a silicon compound represented by Formula (6), characterized by reacting a compound represented by Formula (4) with a compound represented by Formula (5): wherein all of the variables are defined in the specification.

摘要翻译： 一种由式（6）表示的硅化合物的制备方法，其特征在于使由式（4）表示的化合物与式（5）表示的化合物反应：其中所有变量在说明书中定义。

公开(公告)号：US20090294905A1

公开(公告)日：2009-12-03

申请号：US12461136

申请日：2009-08-03

申请人： Kenichi Watanabe

发明人： Kenichi Watanabe

IPC分类号： H01L29/92 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L21/486 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.

公开(公告)号：US07586143B2

公开(公告)日：2009-09-08

申请号：US11339701

申请日：2006-01-26

申请人： Kenichi Watanabe

发明人： Kenichi Watanabe

IPC分类号： H01L27/108

CPC分类号： H01L21/486 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided with a first wiring layer 111, an interlayer insulating film 132 on the first wiring layer 111, a hole 112A formed in the interlayer insulating film, a first metal layer 112 covering the hole 112A, a second metal layer 113 formed in the hole 112A, a dielectric insulating film 135 on the first metal layer 112, and second wiring layers 114-116 on the dielectric insulating film 135, wherein the first metal layer 112 constitutes at least part of the lower electrode, an area, facing the lower electrode, of the second wiring layers 114-116 constitutes the upper electrode, and a capacitor 160 is constructed of the lower electrode, the dielectric insulating film 135 and the upper electrode P1.

摘要翻译： 基板在第一布线层111上设置有第一布线层111，层间绝缘膜132，形成在层间绝缘膜中的孔112A，覆盖孔112A的第一金属层112，形成在第一布线层111上的第二金属层113 孔112A，第一金属层112上的介电绝缘膜135和介电绝缘膜135上的第二布线层114-116，其中第一金属层112构成下电极的至少一部分，面向 第二布线层114-116的下电极构成上电极，电容器160由下电极，电介质绝缘膜135和上电极P1构成。

公开(公告)号：US07538023B2

公开(公告)日：2009-05-26

申请号：US11519052

申请日：2006-09-12

申请人： Kenichi Watanabe

发明人： Kenichi Watanabe

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76828 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.

摘要翻译： 一种制造半导体晶片装置的方法包括以下步骤：（a）在半导体晶片上形成较低的布线图案，所述下布线图案与电路区域中的半导体元件连接; （b）在半导体晶片上形成具有平坦化表面的层间绝缘膜，覆盖下布线图案并具有平坦化表面; 和（c）通过嵌入通孔导体，布线连接到电路区域中连接到下布线图案和配置在通路导体上的布线图案的通孔导体和对应于电路区域以外的周边区域中的布线图案的导体图案 图案和导体图案，导电图案是电隔离的。 该方法可以形成期望的布线结构，并且可以防止有效晶片区域中的有缺陷的器件的百分比的增加。

公开(公告)号：US07484890B2

公开(公告)日：2009-02-03

申请号：US11247586

申请日：2005-10-12

申请人： Takaaki Ikeda ,  Yoshiaki Sakaki ,  Kazuyoshi Kurihara ,  Yoshitaka Waseda ,  Masanori Setsuda ,  Kenichi Watanabe

发明人： Takaaki Ikeda ,  Yoshiaki Sakaki ,  Kazuyoshi Kurihara ,  Yoshitaka Waseda ,  Masanori Setsuda ,  Kenichi Watanabe

IPC分类号： F16C33/58 ,  F16C33/64 ,  B21K1/02 ,  B24B1/00

CPC分类号： F16H53/06 ,  F16C13/006 ,  F16C33/34 ,  F16C2240/54 ,  Y10T29/49679

摘要： There is provided a rolling slide member coming in contact with a mating member in a rolling or sliding manner, wherein a plurality of grooves having an inclination of 0 to 30 degree and a groove depth of 0.5 to 15 μm are formed in a circumferential direction at the time of grinding a contact surface with the mating member. In the contact surface, the axial surface waviness is set to 0.1 or more in the filtered centerline waviness (WCA) and the axial surface roughness is set to 0.7 or more in the ten-point height of roughness profile (Rz) by the grooves 26.

摘要翻译： 提供了一种滚动滑动构件，其以滚动或滑动方式与配合构件接触，其中在圆周方向上形成具有0至30度的倾斜度和0.5至15μm的凹槽深度的多个凹槽 研磨与配合构件的接触表面的时间。 在接触表面中，在过滤的中心线波纹（WCA）中将轴向表面波纹度设定为0.1以上，并且通过槽26在粗糙度轮廓（Rz）的十点高度中将轴向表面粗糙度设定为0.7以上 。

公开(公告)号：US07375170B2

公开(公告)日：2008-05-20

申请号：US11316847

申请日：2005-12-27

申请人： Hisao Oikawa ,  Mikio Yamahiro ,  Koji Ohguma ,  Nobumasa Ootake ,  Kenichi Watanabe ,  Kohji Ohno ,  Yoshinobu Tsujii ,  Takeshi Fukuda

发明人： Hisao Oikawa ,  Mikio Yamahiro ,  Koji Ohguma ,  Nobumasa Ootake ,  Kenichi Watanabe ,  Kohji Ohno ,  Yoshinobu Tsujii ,  Takeshi Fukuda

IPC分类号： C08F4/58

CPC分类号： C07F7/21

摘要： Since the majority of conventional organic/inorganic composite materials are obtained by mechanical blending of a silsesquioxane and an organic polymer or other means, it was extremely difficult to control the structure of the composite as a molecular agglomerate. In order to solve such a problem, the invention is to provide a silicon compound represented by Formula (1). This novel silicon compound has a living radical polymerization initiating ability for addition polymerizable monomers of a wide range. In Formula (1), R1 is hydrogen, an alkyl, an aryl, or an arylalkyl; R2 is an alkyl, phenyl, or cyclohexyl; and A is a group having a polymerization initiating ability for addition polymerizable monomers

摘要翻译： 由于大多数常规的有机/无机复合材料是通过机械共混倍半硅氧烷和有机聚合物或其它方法获得的，所以非常难以控制复合材料的结构作为分子聚集体。 为了解决这个问题，本发明提供一种由式（1）表示的硅化合物。 该新型硅化合物具有广泛范围的可加聚单体的活性自由基聚合引发能力。 在式（1）中，R 1是氢，烷基，芳基或芳基烷基; R 2是烷基，苯基或环己基; A是具有加成聚合性单体的聚合引发能力的基团

公开(公告)号：US20080012147A1

公开(公告)日：2008-01-17

申请号：US11898548

申请日：2007-09-13

申请人： Kenichi Watanabe

发明人： Kenichi Watanabe

IPC分类号： H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

摘要翻译： 半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及掩埋在孔形通孔60和槽形通孔66a中的埋入导体70,72a。 形成沟槽状的通孔66a的宽度小于孔状的通路孔66的宽度。 可以防止掩埋导体的不充分填充和层间绝缘膜的开裂。 导体插头上的步骤可以减少。 因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。