公开(公告)号：US07005701B2

公开(公告)日：2006-02-28

申请号：US10318551

申请日：2002-12-13

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L29/76 ,  H01L39/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06995061B2

公开(公告)日：2006-02-07

申请号：US10779607

申请日：2004-02-18

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Ying-Cheng Chuang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention discloses a multi-bit stacked-type non-volatile memory having a spacer-shaped floating gate and a manufacturing method thereof. The manufacturing method includes forming a patterned dielectric layer containing arsenic on a semiconductor substrate, wherein the patterned dielectric layer defines an opening as an active area. A dielectric spacer is formed on a side wall of the patterned dielectric layer and a gate dielectric layer is formed on the semiconductor substrate. A source/drain region is formed by thermal driving method making arsenic diffusion from the patterned dielectric layer into the semiconductor substrate. A spacer-shaped floating gate is formed on the side wall of the dielectric spacer and the gate dielectric layer. An interlayer dielectric layer is formed on the spacer-shaped floating gate. A control gate is formed on the interlayer dielectric layer and fills the opening of the active area.

公开(公告)号：US06916715B2

公开(公告)日：2005-07-12

申请号：US10694155

申请日：2003-10-27

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/148

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06893919B2

公开(公告)日：2005-05-17

申请号：US10810740

申请日：2004-03-26

申请人： Ying-Cheng Chuang ,  Chung-Lin Huang

发明人： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

公开(公告)号：US20050087823A1

公开(公告)日：2005-04-28

申请号：US10994018

申请日：2004-11-19

申请人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chao-Sung Lai ,  Yung-Meng Huang ,  Ying-Cheng Chuang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7923

摘要： A read-only memory cell (ROM) and a fabrication method thereof. The cell comprises a substrate, a plurality of bit lines, a plurality of bit line oxides, a gate dielectric layer and a word line. The bit lines are formed near the surface of the substrate. The bit line oxides are disposed over the bit lines. The gate dielectric layer is disposed over the substrate between the bit lines and further comprises a silicon-rich oxide layer. The word line is disposed over the bit line oxides and the gate dielectric layer.

摘要翻译： 只读存储单元（ROM）及其制造方法。 电池包括衬底，多个位线，多个位线氧化物，栅极电介质层和字线。 在基板的表面附近形成位线。 位线氧化物位于位线之上。 栅介电层设置在位线之间的衬底上，并且还包括富硅氧化物层。 字线设置在位线氧化物和栅极电介质层之上。

公开(公告)号：US06847068B2

公开(公告)日：2005-01-25

申请号：US10441801

申请日：2003-05-19

申请人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

发明人： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L21/8242

CPC分类号： H01L29/42324 ,  H01L21/28273

摘要： A floating gate with multiple tips and a fabrication method thereof. A semiconductor substrate is provided, on which a patterned hard mask layer is formed, wherein the patterned hard mask layer has an opening. A gate dielectric layer and a first conducting layer with a first predetermined thickness are formed on the bottom of the opening. A spacer is formed on the sidewall of the opening. A conducting spacer is formed on the sidewall of the spacer. The first conducting layer is etched to a second predetermined thickness. A multi-tip floating gate is provided by the first conducting layer and the conducting spacer. A protecting layer is formed in the opening. The patterned hard mask layer, the gate dielectric layer, a portion of the protecting layer, and a portion of the first spacer are etched to expose the surface of the first conducting layer.