公开(公告)号：US20090235145A1

公开(公告)日：2009-09-17

申请号：US12049036

申请日：2008-03-14

申请人： Yutaka Ito ,  Adrian J. Drexler

发明人： Yutaka Ito ,  Adrian J. Drexler

IPC分类号： G11C29/04

CPC分类号： G06F11/106 ,  G11C29/72 ,  G11C2029/0411

摘要： Apparatus, systems, and methods are disclosed, such as those that operate within a memory device to replace one or more selected failing memory cells with one or more repair memory cells and to correct data digits read from other failing memory cells in the memory device using a different method. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 公开了装置，系统和方法，例如在存储器装置内操作以用一个或多个修复存储器单元来替换一个或多个选择的故障存储器单元的装置，系统和方法，以及使用存储器装置中的其它故障存储器单元读取的数据数字来校正 一种不同的方法。 公开了附加装置，系统和方法。

公开(公告)号：US20090116328A1

公开(公告)日：2009-05-07

申请号：US11936628

申请日：2007-11-07

申请人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

发明人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

IPC分类号： G11C5/14

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/144 ,  G11C7/20 ,  G11C11/4072

摘要： Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

摘要翻译： 公开了装置，方法和系统，包括当偏置电压转变到地电位时，防止偏置电压升高到高于存储节点电压的电平的装置，方法和系统。 例如，可以使用第一电压发生器来产生偏置电压以偏置存储器阵列中的存储器单元中的晶体管。 可以利用第二电压发生器来产生板电压。 存储单元可以包括衬底上的晶体管和电容器。 电容器从晶体管的漏极连接到板电压。 存储节点电压位于晶体管的漏极处。 功率控制器可以向第一和第二电压发生器提供关闭信号。 偏压可以从小于零伏的电压转变到地。 偏置电压上升到接地的速率使得偏置电压保持在小于或等于转换时间段内的存储节点电压。

公开(公告)号：US07489580B2

公开(公告)日：2009-02-10

申请号：US11822333

申请日：2007-07-05

申请人： Yutaka Ito ,  Nobuhiro Odaira

发明人： Yutaka Ito ,  Nobuhiro Odaira

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

摘要： A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising: an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature; a dividing circuit which divides an oscillation output of the oscillation circuit; a temperature detector which detects the ambient temperature; and a selector which switches and selects among division outputs with respective frequencies from the dividing circuit based on an output of the temperature detector, and outputs a signal as a reference of the refresh period. The temperature dependence in the oscillation circuit includes a positive temperature coefficient in a predetermined temperature range, and does not include a positive temperature coefficient out of the predetermined temperature range. The selector switches the division outputs out of the predetermined temperature range.

摘要翻译： 一种在刷新DRAM单元时产生刷新周期的刷新周期发生电路，包括：振荡电路，其以与环境温度相关的温度依赖的频率振荡; 分频电路，分频振荡电路的振荡输出; 检测环境温度的温度检测器; 以及选择器，其基于温度检测器的输出，以分频电路的分频输出切换选择，并输出作为刷新周期的基准的信号。 振荡电路中的温度依赖性包括在预定温度范围内的正温度系数，并且不包括超出预定温度范围的正温度系数。 选择器将分割输出切换到预定的温度范围之外。

公开(公告)号：US07464315B2

公开(公告)日：2008-12-09

申请号：US11154467

申请日：2005-06-17

申请人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

发明人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

IPC分类号： H03M13/00

CPC分类号： G11C11/406 ,  G11C2211/4062

摘要： Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

摘要翻译： 公开了具有数据保持操作模式的半导体存储器件。 当执行进入数据保持操作模式的进入时，计算存储器单元的数据的奇偶校验信息，并且在从数据保留操作模式退出时，通过ECC执行对存储器单元的错误校正（ 纠错电路）。 半导体存储装置包括用于从NC引脚标志输出指示半导体存储器件是包括数据保持操作模式的信息的装置，即数据保持操作模式的退出处理正在进行，并且纠错不能 被执行。

公开(公告)号：USD578072S1

公开(公告)日：2008-10-07

申请号：US29274222

申请日：2007-04-05

申请人： Kazunari Hattori ,  Yutaka Ito

设计人： Kazunari Hattori ,  Yutaka Ito

公开(公告)号：US07216198B2

公开(公告)日：2007-05-08

申请号：US10699223

申请日：2003-10-30

申请人： Yutaka Ito ,  Takayuki Aisu ,  Yukihide Suzuki

发明人： Yutaka Ito ,  Takayuki Aisu ,  Yukihide Suzuki

IPC分类号： G06F12/16 ,  G06F12/12

CPC分类号： G11C29/42 ,  G06F11/106 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C2211/4061 ,  G11C2211/4062

摘要： In a semiconductor integrated circuit device, a command decoder is adapted to receive not only an external command but also an internal command. An ECC controller has a command generator and an address generator. When the command decoder decodes an external entry command, the command generator instructs encoding to an ECC-CODEC circuit and the address generator sequentially produces addresses which are supplied to a memory array. The ECC-CODEC circuit produces check bits for error detection/correction with reference to information data of the memory array. Upon completion of an encoding operation of writing the check bits into a predetermined region of the memory array, the ECC controller delivers an end signal to the command decoder as the internal command to make a super self-refresh control circuit start a super self-refresh operation.

摘要翻译： 在半导体集成电路装置中，命令解码器不仅适用于外部命令，而且还接收内部命令。 ECC控制器具有命令生成器和地址生成器。 当命令解码器解码外部输入命令时，命令发生器指令编码到ECC-CODEC电路，并且地址生成器顺序产生提供给存储器阵列的地址。 ECC-CODEC电路参考存储器阵列的信息数据产生用于错误检测/校正的校验位。 在将校验位写入存储器阵列的预定区域的编码操作完成时，ECC控制器将结束信号作为内部命令传送到命令解码器，以使超自我刷新控制电路开始超自我刷新 操作。

公开(公告)号：US06990031B2

公开(公告)日：2006-01-24

申请号：US10231794

申请日：2002-08-29

申请人： Takeshi Hashimoto ,  Yutaka Ito

发明人： Takeshi Hashimoto ,  Yutaka Ito

IPC分类号： G11C7/00

CPC分类号： G11C11/4074 ,  G11C11/406

摘要： In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.

公开(公告)号：US20050281112A1

公开(公告)日：2005-12-22

申请号：US11152762

申请日：2005-06-15

申请人： Yutaka Ito ,  Takeshi Hashimoto

发明人： Yutaka Ito ,  Takeshi Hashimoto

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4062

摘要： Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

摘要翻译： 公开了一种包括错误率测量电路和控制电路的存储器件。 携带BIST电路的误差率测量电路每刷新周期读出并写入用于监视位的区域的数据，以检测刷新周期的错误率（错误计数）。 控制电路进行用于延长和缩短刷新周期的控制，从而实现期望的误码率。 BIST电路发出内部命令和内部地址，并从内部驱动DRAM。 BIST电路写入和读出所需的数据，将监视位与预期值进行比较（错误判定），并对错误进行计数。

公开(公告)号：US06949023B1

公开(公告)日：2005-09-27

申请号：US09555630

申请日：1999-10-01

申请人： Hiroshi Okubo ,  Toshiyuki Koike ,  Yutaka Ito ,  Tetsukazu Nakanishi

发明人： Hiroshi Okubo ,  Toshiyuki Koike ,  Yutaka Ito ,  Tetsukazu Nakanishi

IPC分类号： A63F13/00 ,  A63F13/06 ,  A63F13/10

CPC分类号： A63F13/95 ,  A63F13/10 ,  A63F13/54 ,  A63F2300/206 ,  A63F2300/207 ,  A63F2300/302 ,  A63F2300/6063

摘要： The objective of the present invention is to provide a game machine, a musical tone generation device, and an information storage medium that make it possible to synchronize reproduced sounds and images, even if faults such as skips in those sounds or images occur during the reproduction of sounds and images that have been recorded on optical disk. When a game computation section (30) in this game machine instructs the reproduction of given sound data that has been recorded on an optical disk, based on the game state, sound data (96) that has been read from an optical disk (90) is reproduced by a sound reproduction section (60) and is output to a sound output section (80). During this time, a synchronization processing section (40) performs processing to obtain synchronization with the reproduced sounds, based on synchronization data that was read in together with the sound data, and instructs the images to be reproduced by an image generation section (50) and also the timing at which images are switched. Since image reproduction is based on instructions from the synchronization processing section (40) in this manner, the images can be reproduced in synchronization with the reproduced sounds.

摘要翻译： 本发明的目的是提供一种游戏机，乐音产生装置和信息存储介质，使得即使在再现期间发生这些声音或图像中的跳过等故障，也能够使再现的声音和图像同步 已经记录在光盘上的声音和图像。 当游戏机中的游戏计算部分（30）根据游戏状态指示已经记录在光盘上的给定声音数据的再现时，已经从光盘读取的声音数据（96） 由声音再现部分（60）再现，并输出到声音输出部分（80）。 在此期间，同步处理部（40）基于与声音数据一起读取的同步数据，进行与再现声音的同步的处理，并指示由图像生成部（50）再现的图像， 以及图像切换的定时。 由于图像再现是以这种方式基于来自同步处理部分（40）的指令，所以可以与再现的声音同步地再现图像。

公开(公告)号：US06934212B2

公开(公告)日：2005-08-23

申请号：US10724684

申请日：2003-12-02

申请人： Yutaka Ito

发明人： Yutaka Ito

IPC分类号： G11C11/404 ,  G11C5/14 ,  G11C11/401 ,  G11C11/405 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00 ,  G11C5/06 ,  G11C11/24

CPC分类号： H01L27/10876 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4085 ,  H01L27/108 ,  H01L27/10841

摘要： A simply structured, and highly reliable semiconductor apparatus having a large storage capacity. The apparatus has a plurality of memory cells on one semiconductor substrate, each including a capacitor having first and second electrodes, and a switching device having a control terminal connected to a corresponding word line among a plurality of word lines, and a current channel connected between the first electrode and a corresponding bit line among a plurality of bit lines. When the semiconductor apparatus is in a first mode, an OFF potential of the word lines is set to be a first potential, when the semiconductor apparatus is in a second mode, an OFF potential of the word lines is set to be a second potential, and a current channel of the switching device is set in a direction vertical to the semiconductor substrate.

摘要翻译： 具有大存储容量的简单结构化且高度可靠的半导体装置。 该装置在一个半导体衬底上具有多个存储单元，每个存储单元包括具有第一和第二电极的电容器，以及具有连接到多个字线中的相应字线的控制端子的开关器件，以及连接在 第一电极和多个位线中的相应位线。 当半导体装置处于第一模式时，字线的OFF电位被设置为第一电位，当半导体装置处于第二模式时，字线的OFF电位被设置为第二电位， 并且开关器件的电流通道设置在垂直于半导体衬底的方向上。