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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07464315B2

    公开(公告)日：2008-12-09

    申请号：US11154467

    申请日：2005-06-17

    申请人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

    IPC分类号： H03M13/00

    CPC分类号： G11C11/406 ,  G11C2211/4062

    摘要： Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

    摘要翻译： 公开了具有数据保持操作模式的半导体存储器件。 当执行进入数据保持操作模式的进入时，计算存储器单元的数据的奇偶校验信息，并且在从数据保留操作模式退出时，通过ECC执行对存储器单元的错误校正（ 纠错电路）。 半导体存储装置包括用于从NC引脚标志输出指示半导体存储器件是包括数据保持操作模式的信息的装置，即数据保持操作模式的退出处理正在进行，并且纠错不能 被执行。

    Semiconductor memory device
    2.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20050286330A1

    公开(公告)日：2005-12-29

    申请号：US11154467

    申请日：2005-06-17

    申请人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Eiji Yamasaki ,  Hidetoshi Iwai

    IPC分类号： G11C7/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4062

    摘要： Disclosed is a semiconductor memory device having a data retention operating mode. When an entry into the data retention operating mode is performed, parity information on data of the memory cells is calculated and the error correction on the memory cells is carried out at a time of an exit from the data retention operating mode, by an ECC (Error Correction Circuit). The semiconductor memory device includes means for outputting from an NC pin flag information indicating that the semiconductor memory device is the one including the data retention operating mode, that the exit processing from the data retention operating mode is under way, and that the error correction cannot be performed.

    摘要翻译： 公开了具有数据保持操作模式的半导体存储器件。 当执行进入数据保持操作模式的进入时，计算存储器单元的数据的奇偶校验信息，并且在从数据保留操作模式退出时，通过ECC执行对存储器单元的错误校正（ 纠错电路）。 半导体存储装置包括用于从NC引脚标志输出指示半导体存储器件是包括数据保持操作模式的信息的装置，即数据保持操作模式的退出处理正在进行，并且纠错不能 被执行。

    Data storing method of dynamic RAM and semiconductor memory device
    4.
    发明授权
    Data storing method of dynamic RAM and semiconductor memory device 有权
    动态RAM和半导体存储器件的数据存储方法

    公开(公告)号：US07318183B2

    公开(公告)日：2008-01-08

    申请号：US11399485

    申请日：2006-04-07

    申请人： Yutaka Ito ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Hidetoshi Iwai

    IPC分类号： H03M13/00

    CPC分类号： G06F11/1008 ,  G06F11/106 ,  G06F11/108 ,  G11C7/1006 ,  G11C7/1045 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4062

    摘要： When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

    摘要翻译： 当DRAM进入仅执行数据存储操作的操作模式时，生成并存储用于多个数据的错误检测和校正的校验位。 在通过使用校验位的纠错操作的错误发生的允许范围内的更新周期中执行刷新操作。 在DRAM从数据保持操作模式返回到正常操作模式之前，通过使用数据和校验位来校正错误位。

    Data storing method of dynamic RAM and semiconductor memory device
    6.
    发明授权
    Data storing method of dynamic RAM and semiconductor memory device 有权
    动态RAM和半导体存储器件的数据存储方法

    公开(公告)号：US06697992B2

    公开(公告)日：2004-02-24

    申请号：US09923405

    申请日：2001-08-08

    申请人： Yutaka Ito ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Hidetoshi Iwai

    IPC分类号： G11C2900

    CPC分类号： G06F11/1008 ,  G06F11/106 ,  G06F11/108 ,  G11C7/1006 ,  G11C7/1045 ,  G11C11/406 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4062

    摘要： When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

    摘要翻译： 当DRAM进入仅执行数据存储操作的操作模式时，生成并存储用于多个数据的错误检测和校正的校验位。 在通过使用校验位的纠错操作的错误发生的允许范围内的更新周期中执行刷新操作。 在DRAM从数据保持操作模式返回到正常操作模式之前，通过使用数据和校验位来校正错误位。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06680501B2

    公开(公告)日：2004-01-20

    申请号：US10091488

    申请日：2002-03-07

    申请人： Yutaka Ito ,  Hidetoshi Iwai

    发明人： Yutaka Ito ,  Hidetoshi Iwai

    IPC分类号： H01L27108

    CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

    摘要： A memory cells are arranged at all intersections of a first word line and one line of a bit-line pair and all intersections of a second word line and the other line of the bit-line pair by arranging in parallel the first word line and the second word line consisting of different layers in the row direction with an identical pitch, and, also, alternately arranging the first word line and the second word line at an interval equal to a half of the pitch in the horizontal direction. Moreover, the selection MISFET of the memory cell is formed to have the vertical construction and the bit line located at the upper side of the substrate, where a channel region is formed, is shielded with a conductive film, a part of which forms the gate electrode.

    摘要翻译： 存储单元被布置在第一字线和位线对的一行的所有交点处，并且通过并行排列第一字线和第二字线，布置第二字线和位线对的另一行的所有交点 第二字线由具有相同节距的行方向上的不同层组成，并且还以等于水平方向上的间距的一半的间隔交替地布置第一字线和第二字线。 此外，存储单元的选择MISFET被形成为具有垂直结构，并且位于形成沟道区的衬底的上侧的位线被导电膜屏蔽，其中一部分形成栅极 电极。

    Method of making mask pattern data and process for manufacturing the mask
    10.
    发明授权
    Method of making mask pattern data and process for manufacturing the mask 失效
    制作掩模图案数据的方法和用于制造掩模的工艺

    公开(公告)号：US5458998A

    公开(公告)日：1995-10-17

    申请号：US886403

    申请日：1992-05-21

    申请人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

    发明人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

    IPC分类号： G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  G03F1/84 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

    CPC分类号： G03F1/26 ,  G03F1/29 ,  G03F1/84

    摘要： Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (108) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

    摘要翻译： 可以检查相移掩模的图案数据：（101）通过在实际图案数据层，辅助图案数据层和相移图案数据层中分离和布置相移掩模的图案数据; （102），通过检查和校正实际图案数据层的实际图案的数据; （108）通过从被检查和校正的正确的实际图案数据，辅助图案数据和相移图案数据的合成数据的数据中制作估计传送到半导体晶片的估计图案的数据; 和（104）通过比较估计的图案数据和实际图案数据来检查辅助图案和相移图案的数据。