公开(公告)号：US08339893B2

公开(公告)日：2012-12-25

申请号：US12566862

申请日：2009-09-25

申请人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

发明人： Yuen H. Chan ,  Louis C. Hsu ,  Xu Ouyang ,  Robert C. Wong

IPC分类号： G11C8/00

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.

摘要翻译： 静态随机存取存储器（SRAM）单元包括第一读取端口，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。 静态随机存取存储器（SRAM）阵列包括多个SRAM单元，包括第一读取端口的SRAM单元，第一读取端口具有第一β比率; 和写入端口，所述写入端口具有基本上低于所述第一β比率的第二β比率。

公开(公告)号：US08233331B2

公开(公告)日：2012-07-31

申请号：US12792475

申请日：2010-06-02

申请人： Yuen H. Chan ,  Antonio R. Pelella ,  Richard E. Serton ,  Arthur Tuminaro

发明人： Yuen H. Chan ,  Antonio R. Pelella ,  Richard E. Serton ,  Arthur Tuminaro

IPC分类号： G11C7/06

CPC分类号： H03K19/20

摘要： A compare circuit for comparing a first data word with a second data word includes a plurality of sub-circuits, each having a two-bit static compare stage and a dynamic complex logic stage; a dynamic compare node responsive to respective outputs of the sub-circuits; and an output latch that captures a comparison result in accordance with a logic state of the dynamic compare node. In an exemplary embodiment, a local clock generator provides a single controlling clock signal for clocking the output latch, precharging of the dynamic compare node, and clocking of the dynamic complex logic stage of the sub-circuits.

摘要翻译： 用于比较第一数据字与第二数据字的比较电路包括多个子电路，每个子电路具有两位静态比较级和动态复合逻辑级; 响应于子电路的相应输出的动态比较节点; 以及输出锁存器，其根据动态比较节点的逻辑状态捕获比较结果。 在示例性实施例中，本地时钟发生器提供单个控制时钟信号，用于对输出锁存器进行计时，动态比较节点的预充电以及子电路的动态复合逻辑级的计时。

公开(公告)号：US07936638B2

公开(公告)日：2011-05-03

申请号：US12472510

申请日：2009-05-27

申请人： Yuen H. Chan ,  Michael J. H. Lee ,  Rolf Sautter ,  Tobias Werner

发明人： Yuen H. Chan ,  Michael J. H. Lee ,  Rolf Sautter ,  Tobias Werner

IPC分类号： G11C8/00

CPC分类号： G11C11/417 ,  G11C8/18 ,  H03K7/08

摘要： A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals.

摘要翻译： 脉宽调制电路使用多个可编程路径将其输出线连接到接地连接。 这些路径具有不同数量的串联NFET，以提供不同的下拉速率。 基于编码的控制信号选择所需的可编程路径，其中解码逻辑集成到可编程路径中。 对于每个路径，解码逻辑包括由编码信号之一或其补码控制的至少两个晶体管。 当没有选择可编程路径时，还可以使用默认的接地路径。 例如，两个编码信号可用于在默认路径和三个可编程路径中选择1到4。 将解码逻辑集成到可编程路径中导致较小的总电路面积，导致功率消耗的降低，同时仍然保持编码控制信号的正交优点。

公开(公告)号：US07613944B2

公开(公告)日：2009-11-03

申请号：US11609403

申请日：2006-12-12

申请人： Yuen H. Chan ,  Michael J. Lee

发明人： Yuen H. Chan ,  Michael J. Lee

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer (LCB) to be used throughout an integrated circuit design while still being able to provide differing initial offsets and pulse widths for different local circuitry portions of the integrated circuit design. Delay circuit paths are provided, which provide discreet delay values, within the LCB that can be chained together when the LCB is instantiated to set the initial offset and pulse width values. When an LCB is instantiated in the integrated circuit device design, various ones of the delay circuit paths are connected together with the existing circuit paths of the LCB, i.e. the circuit paths that provide the pre-established offset and pulse width values, in order to set the initial offset and pulse width values for the LCB.

摘要翻译： 提供了一种能够改变初始设置的集成电路设备的可编程本地时钟缓冲器。 说明性实施例允许在整个集成电路设计中使用单一类型的本地时钟缓冲器（LCB），同时仍然能够为集成电路设计的不同本地电路部分提供不同的初始偏移和脉冲宽度。 提供延迟电路路径，其提供LCB内的谨慎延迟值，当LCB被实例化以设置初始偏移和脉冲宽度值时，可以将其链接在一起。 当在集成电路器件设计中实例化LCB时，各种延迟电路路径与LCB的现有电路路径（即提供预先建立的偏移和脉冲宽度值的电路）连接在一起，以便 设置LCB的初始偏移量和脉冲宽度值。

公开(公告)号：US07403412B2

公开(公告)日：2008-07-22

申请号：US11782282

申请日：2007-07-24

申请人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

发明人： Yuen H. Chan ,  Rajiv V. Joshi ,  Donald W. Plass

IPC分类号： G11C11/00 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

公开(公告)号：US07376001B2

公开(公告)日：2008-05-20

申请号：US11250019

申请日：2005-10-13

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

IPC分类号： G11C11/00

CPC分类号： G11C29/50 ,  G11C29/50012

摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator implemented in a row of memory cells and having outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells is operated by the method. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 通过该方法操作在一行存储器单元中实现的具有连接到一个或多个位线的输出的环形振荡器以及与环形振荡器单元基本相同的其它存储器单元。 可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。 形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

公开(公告)号：US07293209B2

公开(公告)日：2007-11-06

申请号：US11054311

申请日：2005-02-09

申请人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella

发明人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella

IPC分类号： G01R31/28

CPC分类号： G01R31/318552

摘要： A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C2 clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C2 is controlled to maintain a constant C2 duty cycle.

摘要翻译： 一种可编程延迟电路，其将C 2时钟信号延迟可变量，即使在L 1锁存器和其L 2锁存器之间存在大的增量时，允许来自L 1锁存器的输出被捕获。 这允许在系统内调整C 2信号，这取决于所需的循环窃取量。 在扫描操作期间，C 2时钟延迟被禁止以防止毛刺，并且延迟的C 2的后沿被控制以保持恒定的C 2占空比。

公开(公告)号：US07170774B2

公开(公告)日：2007-01-30

申请号：US11054479

申请日：2005-02-09

申请人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Uma Srinivasan ,  Arthur D. Tuminaro ,  Jatinder K. Wadhwa

发明人： Yuen H. Chan ,  Ryan T. Freese ,  Antonio R. Pelella ,  Uma Srinivasan ,  Arthur D. Tuminaro ,  Jatinder K. Wadhwa

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/417

摘要： A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.

摘要翻译： 多米诺SRAM阵列恢复脉冲发生系统通过与恢复脉冲相同的本地时钟启动字解码线，从而消除了字线选择的任何种族问题。 该系统允许全局位选择（或列选择）通过释放复位信号（具有最早到达的阵列时钟ckl）来快速激活，同时保证与位解码系统几乎完美的跟踪。 这允许最广泛的写入窗口; 全局列中最早发布预充电选择，仅在位解码系统被禁用后进行复位。

公开(公告)号：US07142064B2

公开(公告)日：2006-11-28

申请号：US10973366

申请日：2004-10-26

申请人： Yuen H. Chan ,  Uma Srinivasan

发明人： Yuen H. Chan ,  Uma Srinivasan

IPC分类号： H03K3/03 ,  G01R23/00 ,  G01R31/26

CPC分类号： G01R31/318364 ,  G01R31/31725 ,  H03K3/0322

摘要： An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read/write circuitry.

摘要翻译： SRAM设计评估电路拓扑结构具有连接到SRAM单元的反相器对的交叉耦合栅极的SRAM单元通过栅极场效应晶体管（FET）的栅极。 该评估电路类型用于全单元实现。 一系列完整的单元在一个环路中互相连接形成一个环形振荡器。 环的输出被分频和测量，以研究单元设计的读写行为。 类似地，其通路门的栅极接地的半电池互相互连以形成环形振荡器，其输出被分频和测量，以帮助隔离通道对存储器功能的影响。 作为硬件环形振荡器连接的修改后的SRAM单元拓扑可用于完全表征SRAM单元设计，而无需使用外设读/写电路。

公开(公告)号：US07084673B2

公开(公告)日：2006-08-01

申请号：US10844298

申请日：2004-05-12

申请人： Yuen H. Chan ,  Antonio R. Pelella ,  Jatinder K. Wadhwa ,  Otto M. Wagner

发明人： Yuen H. Chan ,  Antonio R. Pelella ,  Jatinder K. Wadhwa ,  Otto M. Wagner

IPC分类号： G01R19/00

CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C11/41 ,  G11C11/419 ,  G11C29/32 ,  G11C2029/3202

摘要： A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.

摘要翻译： 用于SRAM的脉冲到静态转换器，其中转换器锁存器由两个交叉耦合的互补FET对组成。 每对的FET在正电压源和地之间将漏极耦合到漏极。 SRAM读出放大器的输出状态作为一个FET对的栅极的输入耦合，由该输入建立的状态通过与另一个FET对的交叉耦合而锁存。