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    Enhanced programmable pulsewidth modulating circuit for array clock generation
    1.
    发明授权
    Enhanced programmable pulsewidth modulating circuit for array clock generation 失效
    用于阵列时钟产生的增强可编程脉宽调制电路

    公开(公告)号：US07936638B2

    公开(公告)日：2011-05-03

    申请号：US12472510

    申请日：2009-05-27

    申请人： Yuen H. Chan ,  Michael J. H. Lee ,  Rolf Sautter ,  Tobias Werner

    发明人： Yuen H. Chan ,  Michael J. H. Lee ,  Rolf Sautter ,  Tobias Werner

    IPC分类号： G11C8/00

    CPC分类号： G11C11/417 ,  G11C8/18 ,  H03K7/08

    摘要： A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals.

    摘要翻译： 脉宽调制电路使用多个可编程路径将其输出线连接到接地连接。 这些路径具有不同数量的串联NFET，以提供不同的下拉速率。 基于编码的控制信号选择所需的可编程路径，其中解码逻辑集成到可编程路径中。 对于每个路径，解码逻辑包括由编码信号之一或其补码控制的至少两个晶体管。 当没有选择可编程路径时，还可以使用默认的接地路径。 例如，两个编码信号可用于在默认路径和三个可编程路径中选择1到4。 将解码逻辑集成到可编程路径中导致较小的总电路面积，导致功率消耗的降低，同时仍然保持编码控制信号的正交优点。

    ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK GENERATION
    2.
    发明申请
    ENHANCED PROGRAMMABLE PULSEWIDTH MODULATING CIRCUIT FOR ARRAY CLOCK GENERATION 失效
    用于阵列时钟发生的增强可编程脉宽调制电路

    公开(公告)号：US20100302895A1

    公开(公告)日：2010-12-02

    申请号：US12472510

    申请日：2009-05-27

    申请人： Yuen H. Chan ,  Michael J. H. Lee ,  Rolf Sautter ,  Tobias Werner

    发明人： Yuen H. Chan ,  Michael J. H. Lee ,  Rolf Sautter ,  Tobias Werner

    IPC分类号： G11C8/18 ,  H03K17/00 ,  H03K7/08

    CPC分类号： G11C11/417 ,  G11C8/18 ,  H03K7/08

    摘要： A pulsewidth modulation circuit uses a plurality of programmable paths to connect its output line to ground connections. The paths have different numbers of serially-connected NFETs to provide different pulldown rates. A desired programmable paths is selected based on encoded control signals, with decode logic integrated into the programmable paths. The decode logic includes, for each path, at least two transistors controlled by one of the encoded signals or their complements. A default path to ground may also be provided for use when none of the programmable paths is selected. For example, two encoded signals may be used to select 1-in-4 among the default path and three programmable paths. Integration of the decode logic into the programmable paths results in smaller overall circuit area, leading to reduced power usage, while still retaining the orthogonal benefit of encoded control signals.

    摘要翻译： 脉宽调制电路使用多个可编程路径将其输出线连接到接地连接。 这些路径具有不同数量的串联NFET，以提供不同的下拉速率。 基于编码的控制信号选择所需的可编程路径，其中解码逻辑集成到可编程路径中。 对于每个路径，解码逻辑包括由编码信号之一或其补码控制的至少两个晶体管。 当没有选择可编程路径时，还可以使用默认的接地路径。 例如，两个编码信号可用于在默认路径和三个可编程路径中选择1到4。 将解码逻辑集成到可编程路径中导致较小的总电路面积，导致功率消耗的降低，同时仍然保持编码控制信号的正交优点。

    Low Power Programmable Clock Delay Generator with Integrated Decode Function
    4.
    发明申请
    Low Power Programmable Clock Delay Generator with Integrated Decode Function 失效
    具有集成解码功能的低功耗可编程时钟延迟发生器

    公开(公告)号：US20090267667A1

    公开(公告)日：2009-10-29

    申请号：US12109728

    申请日：2008-04-25

    申请人： Yuen H. Chan ,  Rolf Sautter ,  Michael J. Lee ,  Juergen Pille

    发明人： Yuen H. Chan ,  Rolf Sautter ,  Michael J. Lee ,  Juergen Pille

    IPC分类号： H03L7/00

    CPC分类号： H03K5/04 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00058

    摘要： A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.

    摘要翻译： 可编程本地时钟缓冲器在时钟输入和延迟时钟输出之间具有单个反相器。 晶体管开关在时钟信号发送状态和非发送状态之间调制单个逆变器级。 延迟选择位的组合控制逆变器相对于经由晶体管开关的时钟输入的发送状态的开始和结束的定时。

    Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry
    6.
    发明申请
    Tri-State Circuit Element Plus Tri-State-Multiplexer Circuitry 审中-公开
    三态电路元件加三态复用器电路

    公开(公告)号：US20080258769A1

    公开(公告)日：2008-10-23

    申请号：US12060537

    申请日：2008-04-01

    申请人： Dirk Franger ,  Rolf Sautter ,  Tobias Werner ,  Pascal Witte

    发明人： Dirk Franger ,  Rolf Sautter ,  Tobias Werner ,  Pascal Witte

    IPC分类号： H03K19/00

    CPC分类号： H03K17/005 ,  H03K19/0002 ,  H03K19/0013

    摘要： A Tri-State circuit element (100) composed of Complementary Metal Oxide Semiconductor (CMOS)—devices is described. Said Tri-State circuit element (100) having a data signal input terminal (102) for receiving a data signal, an enable signal input terminal (104) for receiving an enable signal, and an output signal terminal (106) for providing an output signal. Furthermore a Tri-State-Multiplexer circuitry (300) composed of such Tri-State circuit elements (100) is described.

    摘要翻译： 描述由互补金属氧化物半导体（CMOS）器件组成的三态电路元件（100）。 所述三态电路元件（100）具有用于接收数据信号的数据信号输入端（102），用于接收使能信号的使能信号输入端（104）和用于提供输出的输出信号端（106） 信号。 此外，描述了由这种三态电路元件（100）组成的三态复用器电路（300）。

    Power saving by disabling cyclic bitline precharge
    8.
    发明授权
    Power saving by disabling cyclic bitline precharge 有权
    通过禁用循环位线预充电节电

    公开(公告)号：US07295481B2

    公开(公告)日：2007-11-13

    申请号：US10711982

    申请日：2004-10-18

    申请人： Juergen Pille ,  Rolf Sautter ,  Christian Schweizer ,  Klaus Thumm

    发明人： Juergen Pille ,  Rolf Sautter ,  Christian Schweizer ,  Klaus Thumm

    IPC分类号： G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/22 ,  G11C2207/2227

    摘要： A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether a next access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal is combined with an external control signal indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal. The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.

    摘要翻译： 一种访问由位线预充电电路操作的动态硬件存储器块内的存储器单元的方法和系统，其中通过激活补充位线执行差分读/写访问操作。 通过确定当前访问操作之后的下一个访问操作是读取还是写入访问，并且仅当读取操作遵循当前访问操作时才执行阵列的位线的预充电来实现功耗的降低。 常规的预充电控制信号与指示下一个周期是否为读周期的外部控制信号组合。 两个信号的组合可以用作例如简单与门的输入以产生有效的预充电信号。 只有当这些位线用于在相应的下一周期中的读取访问时，有效的预充电信号才允许位线预充电。

    Enhanced power savings for memory arrays
    9.
    发明授权
    Enhanced power savings for memory arrays 有权
    增强内存阵列功耗

    公开(公告)号：US08659963B2

    公开(公告)日：2014-02-25

    申请号：US13343996

    申请日：2012-01-05

    申请人： Osama Dengler ,  Stefan Payer ,  Philipp Salz ,  Rolf Sautter

    发明人： Osama Dengler ,  Stefan Payer ,  Philipp Salz ,  Rolf Sautter

    IPC分类号： G11C7/00

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

    摘要： A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.

    摘要翻译： 提供了存储器阵列，其包括多个全局位线，使得每个位线耦合到多个存储器单元。 存储器阵列还包括多个预充电逻辑，使得每个预充电逻辑耦合到多个全局位线中的相关联的全局位线。 存储器阵列中的识别逻辑耦合到多个预充电逻辑。 识别逻辑在每个时钟周期向多个预充电逻辑的子集提供预充电使能信号，使得预充电逻辑的子集将其相关联的全局位线子集预充电到电压源的电压电平，从而降低功耗 的存储器阵列。

    Enhanced Power Savings for Memory Arrays
    10.
    发明申请
    Enhanced Power Savings for Memory Arrays 有权
    增强内存阵列功耗

    公开(公告)号：US20130176795A1

    公开(公告)日：2013-07-11

    申请号：US13343996

    申请日：2012-01-05

    申请人： Osama Dengler ,  Stefan Payer ,  Philipp Salz ,  Rolf Sautter

    发明人： Osama Dengler ,  Stefan Payer ,  Philipp Salz ,  Rolf Sautter

    IPC分类号： G11C7/12 ,  G11C7/10

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

    摘要： A memory array is provided that comprises a plurality of global bit lines such that each bit line is coupled to a plurality of memory cells. The memory array further comprises a plurality of precharge logic such that each precharge logic is coupled to an associated global bit line in the plurality of global bit lines. Identification logic in the memory array is coupled to the plurality of precharge logic. The identification logic provides a precharge enable signal to a subset of the plurality of precharge logic on each clock cycle such that the subset of precharge logic precharges its associated subset of global bit lines to a voltage level of a voltage source, thereby reducing the power consumption of the memory array.

    摘要翻译： 提供了存储器阵列，其包括多个全局位线，使得每个位线耦合到多个存储器单元。 存储器阵列还包括多个预充电逻辑，使得每个预充电逻辑耦合到多个全局位线中的相关联的全局位线。 存储器阵列中的识别逻辑耦合到多个预充电逻辑。 识别逻辑在每个时钟周期向多个预充电逻辑的子集提供预充电使能信号，使得预充电逻辑的子集将其相关联的全局位线子集预充电到电压源的电压电平，由此降低功耗 的存储器阵列。