公开(公告)号：US07298653B1

公开(公告)日：2007-11-20

申请号：US10873872

申请日：2004-06-21

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC分类号： G11C11/34

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C16/12 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004

摘要： In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.

摘要翻译： 在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。 通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。

公开(公告)号：US07180133B1

公开(公告)日：2007-02-20

申请号：US11016147

申请日：2004-12-17

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski ,  Philipp Lindorfer

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/7835

摘要： In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.

摘要翻译： 在具有减少的热载流子劣化的高电压LDMOS的方法和结构中，消除了厚场氧化物，并且通过在漏极阱中包括相邻的p +和n +区域而将这些区域彼此短路，或者通过 包括漏极阱中的p +区，并将其偏压到相对于源极电压的正电压。

公开(公告)号：US07102117B2

公开(公告)日：2006-09-05

申请号：US10863058

申请日：2004-06-08

申请人： Peter J. Hopper ,  Philipp Lindorfer ,  Mark W. Poulter ,  Yuri Mirgorodski

发明人： Peter J. Hopper ,  Philipp Lindorfer ,  Mark W. Poulter ,  Yuri Mirgorodski

IPC分类号： H01L27/00

CPC分类号： H01L27/14609 ,  H04N5/35572 ,  H04N5/361 ,  H04N5/37452

摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

摘要翻译： 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间，可以将光电二极管暴露于​​光子，以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。

公开(公告)号：US06862216B1

公开(公告)日：2005-03-01

申请号：US10880176

申请日：2004-06-29

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Vladislav Vashchenko

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/861 ,  G11C16/06

CPC分类号： G11C16/0416 ,  H01L29/7881 ,  H01L29/8616

摘要： A non-volatile memory cell including a gated diode and a single readout transistor, methods for programming and reading out such a cell, and a memory including an array of such cells. The readout transistor is an MOS transistor. The transistor and gated diode are formed in a volume of semiconductor material of one type, and share a source region, a control gate, and a floating gate. The transistor has a drain region formed of semiconductor material of one type and the diode has a drain region formed of semiconductor material of the opposite type.

摘要翻译： 包括门控二极管和单个读出晶体管的非易失性存储单元，用于编程和读出这样的单元的方法以及包括这种单元阵列的存储器。 读出晶体管是MOS晶体管。 晶体管和门控二极管形成为一种类型的半导体材料的体积，并且共享源极区域，控制栅极和浮动栅极。 晶体管具有由一种类型的半导体材料形成的漏极区域，并且二极管具有由相反类型的半导体材料形成的漏极区域。

公开(公告)号：US06586302B1

公开(公告)日：2003-07-01

申请号：US09931477

申请日：2001-08-16

申请人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

发明人： Peter J. Hopper ,  Yuri Mirgorodski ,  Chin Miin Shyu ,  David Tsuei ,  Peter Johnson ,  Alexander H. Owens

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is utilized to provide a floating gate having sharply defined tip characteristics. A first insulating layer is formed over a substrate. A conductive material is formed over the first insulating layer. A trench is defined in the conductive layer. This trench is filled with an oxide which is used as a mask to define tips of the floating gate during an etching process which defines the edges of the floating gate. After the floating gate has been etched, a tunneling oxide deposited over the floating gate. A conductive material is then formed over the tunneling oxide.

摘要翻译： 公开了一种制造电可编程和可擦除存储单元的方法。 具体地说，利用浅沟槽隔离型技术产生浮置栅极的方法用于提供具有尖锐定义的尖端特性的浮动栅极。 第一绝缘层形成在衬底上。 在第一绝缘层上形成导电材料。 在导电层中限定沟槽。 该沟槽填充有氧化物，其用作掩模以在限定浮动栅极的边缘的蚀刻工艺期间限定浮置栅极的尖端。 在浮栅被蚀刻之后，沉积在浮栅上的隧道氧化物。 然后在隧道氧化物上形成导电材料。

公开(公告)号：US06528844B1

公开(公告)日：2003-03-04

申请号：US10000661

申请日：2001-10-31

申请人： Peter J. Hopper ,  Yuri Mirgorodski

发明人： Peter J. Hopper ,  Yuri Mirgorodski

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A split-gate FLASH memory cell is formed with a floating gate that has a tip in the middle of the floating gate. The method of the present invention forms the tip to have a substantially constant radius of curvature, tip angle, and distance to the overlying tunneling oxide. As a result, the tip of the present invention increases the localized enhancement of the electric field.

摘要翻译： 分离栅极FLASH存储单元形成有浮动栅极，该浮动栅极在浮动栅极的中间具有尖端。 本发明的方法形成了具有基本上恒定的曲率半径，尖角以及与上覆隧道氧化物的距离的尖端。 结果，本发明的尖端增加了电场的局部增强。

公开(公告)号：US08554529B2

公开(公告)日：2013-10-08

申请号：US11998478

申请日：2007-11-30

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  William French ,  Philipp Lindorfer

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  William French ,  Philipp Lindorfer

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of simulating an integrated circuit device under test (DUT) is provided, wherein the DUT includes a plurality of terminals. For each terminal of the DUT, a probe pulse is applied to the terminal and a reaction is recorded at the terminal and each of the other terminals to obtain values representative of reactive tails for the terminal. For each terminal, the values representative of the reactive tails obtained for the terminal are stored as an entry of a look-up table. Each entry includes n+x fields, wherein n represents a number of arguments in the entry and x represents a number of functions in the entry. For each terminal, a signal value at a selected time step is calculated.

摘要翻译： 提供了一种模拟被测集成电路器件（DUT）的方法，其中DUT包括多个端子。 对于DUT的每个端子，将探头脉冲施加到端子，并且在端子和每个其他端子处记录反应以获得表示端子的反应尾部的值。 对于每个终端，代表为终端获得的反应式尾部的值被存储为查找表的条目。 每个条目包括n + x个字段，其中n表示条目中的参数数，x表示条目中的一些函数。 对于每个终端，计算所选时间步长处的信号值。

公开(公告)号：US07651913B2

公开(公告)日：2010-01-26

申请号：US12012545

申请日：2008-02-04

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  Vladislav Vashchenko

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L29/42324

摘要： An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

摘要翻译： 在非易失性存储器（NVM）单元结构中提供电屏蔽，以在编程操作期间保护电池的浮动栅极免受在浮动栅极附近的电荷再分配的任何影响。 可以从覆盖浮动栅极的第二多晶硅层或其他导电材料产生屏蔽。 屏蔽可能接地。 或者，其可以连接到电池的控制栅电极，从而在浮栅和控制栅之间形成更好的耦合。 屏蔽罩完全不需要覆盖浮动栅极，如果与围绕浮动栅极的电介质层的耦合减小，则实现必要的保护效果。

公开(公告)号：US07651897B2

公开(公告)日：2010-01-26

申请号：US11869857

申请日：2007-10-10

申请人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski

发明人： Vladislav Vashchenko ,  Peter J. Hopper ,  Yuri Mirgorodski

IPC分类号： H01L21/86

CPC分类号： H01L23/367 ,  H01L21/84 ,  H01L27/0211 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent to the transistor). The chip can be implemented by a semiconductor on insulator (SOI) process and can include at least one bipolar or MOS transistor, an insulator underlying the transistor, a semiconductor substrate underlying the insulator, and a metal heat flow path extending between a terminal of the transistor through the insulator to the substrate. Preferably, the metal heat flow path is a metal interconnect formed by a process step (or steps) of the same type performed to produce other metal interconnects of the chip.

摘要翻译： 一种用于制造具有在其晶体管的端子之间延伸的金属热流路和芯片的体半导体材料（例如，从端子到其上形成晶体管的衬底或者到半导体器件的主体）的芯片的制造方法 与晶体管相邻）。 该芯片可以通过半导体绝缘体（SOI）工艺来实现，并且可以包括至少一个双极或MOS晶体管，晶体管下面的绝缘体，绝缘体下面的半导体衬底，以及在绝缘体的端子之间延伸的金属热流路径 晶体管通过绝缘体到基板。 优选地，金属热流路径是通过对芯片的其他金属互连进行的相同类型的工艺步骤（或步骤）形成的金属互连。

公开(公告)号：US20090144035A1

公开(公告)日：2009-06-04

申请号：US11998478

申请日：2007-11-30

申请人： Yuri Mirgorodski ,  Peter J. Hopper ,  William French ,  Philipp Lindorfer

发明人： Yuri Mirgorodski ,  Peter J. Hopper ,  William French ,  Philipp Lindorfer

IPC分类号： G06G7/48

CPC分类号： G06F17/5036

摘要： A modified “black box” integrated circuit simulation model is provided that is based only upon on the external steady-state and transient characteristics of a device under test (DUT). The method utilizes probe pulses as well as steady-state I-V and C-V look-up tables. In contrast to conventional black box simulation models, which support only steady-state and small signal frequency analysis, the disclosed method also supports large signal transient analysis.

摘要翻译： 提供了一种基于被测器件（DUT）的外部稳态和瞬态特性的改进的“黑匣子”集成电路仿真模型。 该方法利用探头脉冲以及稳态I-V和C-V查找表。 与仅支持稳态和小信号频率分析的常规黑盒仿真模型相反，所公开的方法还支持大信号瞬态分析。