公开(公告)号：US20110269281A1

公开(公告)日：2011-11-03

申请号：US12768895

申请日：2010-04-28

Applicant: Paul A. Clifton

Inventor： Paul A. Clifton

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/7849

Abstract: Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed. For example, implanting ions through the surface silicon layer on either side of the gate structure of the preferred FET implementation into an underlying stressor layer can induce strain in a channel region of the FET. This process can begin with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used.

Abstract translation: 用于制造场效应晶体管的过程放松埋置的应力层以在埋层应力层上方的硅表面层中引起应变。 埋置的应力层松弛，并且表面层通过注入到至少埋置的应力层中，优选地在被压应的表面层的一部分的两侧被应变。 例如，通过优选FET实施方式的栅极结构的任一侧的表面硅层将离子注入到下面的应力层中可以在FET的沟道区域中引起应变。 该工艺可以以具有适当厚度和锗浓度的掩埋硅锗层的硅或绝缘体上硅衬底开始。 可以使用其他应力源材料。

公开(公告)号：US20110092047A1

公开(公告)日：2011-04-21

申请号：US12687646

申请日：2010-01-14

Applicant: R. Stockton Gaines ,  Daniel J. Connelly ,  Paul A. Clifton

Inventor： R. Stockton Gaines ,  Daniel J. Connelly ,  Paul A. Clifton

IPC: H01L21/762

CPC classification number: H01L29/1054 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/78 ,  H01L29/7846

Abstract: The present invention relates to creating an active layer of strained semiconductor using a combination of buried and sacrificial stressors. That is, a process can strain an active semiconductor layer by transferring strain from a stressor layer buried below the active semiconductor layer and by transferring strain from a sacrificial stressor layer formed above the active semiconductor layer. As an example, the substrate may be silicon, the buried stressor layer may be silicon germanium, the active semiconductor layer may be silicon and the sacrificial stressor layer may be silicon germanium. Elastic edge relaxation is preferably used to efficiently transfer strain to the active layer.

Abstract translation: 本发明涉及使用掩埋和牺牲应力源的组合来产生应变半导体的有源层。 也就是说，工艺可以通过从埋在有源半导体层下面的应力层传输应变并且通过从形成在有源半导体层上方的牺牲应力层转移应变而使活性半导体层变形。 作为示例，衬底可以是硅，所述埋置的应力层可以是硅锗，所述有源半导体层可以是硅，并且所述牺牲应力层可以是硅锗。 优选使用弹性边缘松弛以有效地将应变传递到活性层。

公开(公告)号：US07902029B2

公开(公告)日：2011-03-08

申请号：US11166286

申请日：2005-06-23

Applicant: Daniel E. Grupp ,  Daniel J. Connelly ,  Paul A. Clifton ,  Carl M. Faulkner

Inventor： Daniel E. Grupp ,  Daniel J. Connelly ,  Paul A. Clifton ,  Carl M. Faulkner

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/78618 ,  H01L2029/7858

Abstract: Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.

Abstract translation: 用于形成自对准，沉积的源极/漏极，绝缘栅极，晶体管，特别是FET的工艺。 通过在凹部中沉积源/漏，使得其仅保留在凹槽中，源/漏可以形成为与这种器件的栅极和/或沟道自对准。 例如，在一个这样的过程中，可以形成晶体管的栅极结构，并且在围绕栅极结构的材料中形成凹槽，以便与栅极结构的边缘对准。 随后，源极/漏极导电材料可以沉积在凹部中。 这种源极/漏极导电材料在一些情况下可以沉积成层，其中一个或多个这样的层在其沉积之后被平坦化。 以这种方式，导电材料保持在凹槽的边界内。

公开(公告)号：US07884003B2

公开(公告)日：2011-02-08

申请号：US12197996

申请日：2008-08-25

Applicant: Daniel E. Grupp ,  Daniel J. Connelly

Inventor： Daniel E. Grupp ,  Daniel J. Connelly

IPC: H01L21/28 ,  H01L21/44

CPC classification number: H01L29/456 ,  H01L21/28537 ,  H01L29/0895 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/806 ,  H01L29/812 ,  H01L29/872

Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 Ω-μm2 or even less than or equal to 1 Ω-μm2 for the electrical device.

Abstract translation: 一种电气装置，其中界面层设置在与金属和Si基半导体接触并与之接触之间，所述界面层具有有效降低半导体费米能级的厚度，同时仍允许电流在金属 和半导体。 界面层可以包括钝化材料层（例如由氮，氧，氮氧化物，砷，氢和/或氟制成），有时还包括分离层。 在一些情况下，界面层可以是半导体钝化材料的单层。 界面层厚度对应于电气装置的最小比接触电阻小于或等于10Ω-OHgr，或甚至小于或等于1Ω·cmgr·-m2。

公开(公告)号：US07883980B2

公开(公告)日：2011-02-08

申请号：US11403185

申请日：2006-04-11

Applicant: Daniel E. Grupp ,  Daniel J. Connelly

Inventor： Daniel E. Grupp ,  Daniel J. Connelly

IPC: H01L21/336

CPC classification number: H01L29/47 ,  H01L21/28537 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0895 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66143 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66848 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/812 ,  H01L29/8126 ,  Y10S438/958

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 Ω-μm2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface. Also, the interface layer may include a separation layer of a material different than the passivating material. Where used, the separation layer has a thickness sufficient to reduce effects of metal-induced gap states in the semiconductor channel.

Abstract translation: 晶体管包括设置在栅极附近并且在源极和漏极之间的电气路径中的半导体沟道，其中所述沟道和源极或漏极中的至少一个由界面层分开以形成沟道界面层 源极/漏极结，其中半导体通道的费米能级在接合点附近的区域中被取代，并且该结具有小于约1000Ω的比接触电阻。 界面层可以包括通道的半导体的钝化材料，例如氮化物，氟化物，氧化物，氧氮化物，氢化物和/或砷化物。 在一些情况下，界面层基本上由被配置为消除通道的半导体的费米能级的单层或者足以终止半导体通道的全部或足够数量的悬挂键以达到化学稳定性的钝化材料的量 的表面。 此外，界面层可以包括与钝化材料不同的材料的分离层。 在使用时，分离层具有足以减少半导体通道中金属诱发的间隙状态的影响的厚度。

公开(公告)号：US07816240B2

公开(公告)日：2010-10-19

申请号：US11678397

申请日：2007-02-23

Applicant: Carl M. Faulkner ,  Daniel J. Connelly ,  Paul A. Clifton ,  Daniel E. Grupp

Inventor： Carl M. Faulkner ,  Daniel J. Connelly ,  Paul A. Clifton ,  Daniel E. Grupp

IPC: H01L21/28

CPC classification number: H01L21/28537 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684

Abstract: A metal source/drain field effect transistor is fabricated such that the source/drain regions are deposited, multilayer structures, with at least a second metal deposited on exposed surfaces of a first metal.

Abstract translation: 制造金属源极/漏极场效应晶体管，使得源极/漏极区域被沉积，多层结构，至少第二金属沉积在第一金属的暴露表面上。

公开(公告)号：US20100195774A1

公开(公告)日：2010-08-05

申请号：US12365805

申请日：2009-02-04

Applicant: Fernando Lopez de Victoria

Inventor： Fernando Lopez de Victoria

IPC: H04L27/00 ,  H04B1/10

CPC classification number: H04L25/025 ,  H04B7/0848 ,  H04L25/0212 ,  H04L25/0224 ,  H04L27/2647

Abstract: An OFDM system generates a channel estimate in the time domain for use in either a frequency domain equalizer or in a time domain equalizer. Preferably channel estimation is accomplished in the time domain using a locally generated reference signal. The channel estimator generates an initial estimate from a cross correlation between the time domain reference signal and an input signal input to the receiver and generates at least one successive channel estimate. Preferably the successive channel estimate is determined by vector addition (or subtraction) to the initial channel estimate. The at least one successive channel estimate reduces the minimum mean square error of the estimate with respect to a received signal.

Abstract translation: OFDM系统在时域中产生用于频域均衡器或时域均衡器中的信道估计。 优选地，使用本地生成的参考信号在时域中完成信道估计。 信道估计器根据时域参考信号和输入到接收机的输入信号之间的互相关产生初始估计，并产生至少一个连续的信道估计。 优选地，通过对初始信道估计的向量相加（或减法）来确定连续信道估计。 所述至少一个连续的信道估计相对于接收到的信号减小估计的最小均方误差。

公开(公告)号：US20100047977A1

公开(公告)日：2010-02-25

申请号：US12564387

申请日：2009-09-22

Applicant: Paul A. Clifton

Inventor： Paul A. Clifton

IPC: H01L21/8238

CPC classification number: H01L29/7846 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636

Abstract: A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations.

Abstract translation: 在硅衬底上生长SiGe的薄覆层外延层，以在生长平面中具有双轴压应力。 硅的薄外延层沉积在SiGe层上，SiGe层的厚度小于其临界厚度。 随后通过外延层制造浅沟槽，使得应变能被重新分布，使得SiGe层中的压缩应变被弹性地部分松弛，并且一定程度的拉伸应变被诱导到相邻的硅层。 因为在硅层中诱导拉伸应变的这种方法本质上是弹性的，所以可以实现期望的应变而不会形成失配位错。

公开(公告)号：US07612365B2

公开(公告)日：2009-11-03

申请号：US12036969

申请日：2008-02-25

Applicant: Paul A. Clifton

Inventor： Paul A. Clifton

IPC: H01L31/0336 ,  H01L21/00

CPC classification number: H01L29/7846 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636

Abstract: A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations.

Abstract translation: 在硅衬底上生长SiGe的薄覆层外延层，以在生长平面中具有双轴压应力。 硅的薄外延层沉积在SiGe层上，SiGe层的厚度小于其临界厚度。 随后通过外延层制造浅沟槽，使得应变能被重新分布，使得SiGe层中的压缩应变被弹性地部分松弛，并且一定程度的拉伸应变被诱导到相邻的硅层。 因为在硅层中诱导拉伸应变的这种方法本质上是弹性的，所以可以实现期望的应变而不会形成失配位错。

公开(公告)号：US07599426B2

公开(公告)日：2009-10-06

申请号：US10894913

申请日：2004-07-19

Applicant: Alvin M. Despain

Inventor： Alvin M. Despain

IPC: H04B1/00

CPC classification number: H04B1/7097 ,  H04L25/03038

Abstract: A code division multiple access (CDMA) radio system uses an adaptive filter in a receiver to mitigate multipath radio propagation and to filter out interfering signals. Characteristics of an initial stage of the filter preferably are determined by cross correlation of a generated pilot signal and the input signal with the integration of the correlation performed over a time period selected to be an integral number of symbol periods. The integration causes the portions of the cross correlation corresponding to the user subchannels to average substantially to zero, so that the pilot channel signal correlation is the primary contribution to the signal used to characterize the channel to establish the coefficients of the adaptive filter for the receiver.

Abstract translation: 码分多址（CDMA）无线电系统在接收机中使用自适应滤波器来减轻多径无线电传播并滤除干扰信号。 优选地，滤波器的初始阶段的特性通过所生成的导频信号和输入信号的互相关相关来确定，其中所选择的相关时间选择为整数个符号周期。 整合使得与用户子信道相对应的互相关的部分基本上平均为零，使得导频信道信号相关性是用于表征信道的信号的主要贡献，以建立用于接收机的自适应滤波器的系数 。