Abstract:
An antenna system has N antenna units stacked on a mast. Each unit has elements for responding to, e.g., GPS signals, and a phasing network that produces mutually orthogonal primary and auxiliary pattern modes at corresponding mode ports of the unit. A number of power dividers are each associated with a different mode, and each divider has N input ports coupled to the associated mode port of a corresponding antenna unit. The power divider associated with the primary pattern mode produces a reference beam and an auxiliary beam, and remaining power dividers produce different auxiliary beams. All beams have approximately both a common phase center and a common group delay center. An adaptive processor combines the reference and selected auxiliary beams to obtain a composite antenna reception pattern in which nulls are inserted at certain angles to suppress interfering signals, without degrading authentic signals arriving at other angles.
Abstract:
The system and method for clock synchronization, or calibration, for use in high speed asynchronous serial interfaces. The system and method is automatic, on-line, and occurs in real-time. The process of synchronization may also be started by a user. The calibration scheme is a form of adaptive filtering using 8B10B encoding. Once idle traffic is 8B10B encoded it becomes a stream of K28.5 characters. These characters are used to tune a clock frequency. The process stops, and two devices are synchronized, when the number of idle K28.5 traffic samples are uniformly approximately identical for any of two successive sample intervals.
Abstract:
A multi-chip module hybrid integrated circuit (MCM-HIC) provides cold spare support to an apparatus comprising a plurality of ICs and/or other circuits that are not cold spare compliant. At least one core IC and at least one cold spare chiplet are installed on an interconnecting substrate having a plurality of power zones to which power can be applied and withdrawn as needed. When powered, the cold spare chiplets serve as mediators and interfaces between the non cold spare compliant circuits. When the cold spare chiplets are at least partly unpowered, they protect all interconnected circuits, and ensure that interconnected circuits that remain powered are not hindered by unpowered interconnected circuits. Cold spare chiplets can extend across boundaries between power zones. External circuits can be exclusively interfaced to a subset of the power zones. Separate power circuits within a power zone can be sequenced during application and withdrawal of power.
Abstract:
Disclosed is a system for a weapon sight for aiming a target. The system includes a controller unit configured to initiate an electronic zoom calibration mode, locate a red dot of a day view optic, cause a line of sight to the target unperturbed, electronically superimpose a reticle of the weapon sight onto a thermal image of the target, store information corresponding to a location of the reticle when the reticle is allowed to coincide with the located red dot, and write a pixel corresponding to the stored information of the location of the reticle to a pixel written corresponding to a location of the reticle in a non-electronic zoom mode. The system also includes a memory unit communicably coupled to the controller unit. Further disclosed are a weapon sight and a method for aiming a target using electronic zoom calibration.
Abstract:
Rather than using balanced transmission lines the stimulated response due to nuclear quadrupole resonance can be detected using a single monopole, with multiple monopoles improving substance detection.
Abstract:
An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.
Abstract:
An uncooled infrared sensor can be used for a plurality of applications such as fire fighting, surveilling a border or any desired area, and limb sounding. The uncooled infrared sensor includes manually or automatically adjustable optics that receive an electromagnetic signal, focus the electromagnetic signal and provide a focused electromagnetic signal to a focal plane array. The focal plane array includes a plurality of detector devices disposed in rows and columns to form the focal plane array. Each detector device is constructed so as to have a reduced pitch and provide a maximum number of detectors within a minimum square area of the focal plane array. Each detector device detects the focused electromagnetic signal incident upon it, converts the focused electromagnetic signal into a sensed signal and outputs the sensed signal so that the focal plane array provides a plurality of sensed signals. The sensor also includes a focal plane array processor that has a plurality of cells corresponding to the plurality of detector devices. The focal plane array processor receives the plurality of sensed signals, processes the plurality of sensed signals to correct for any gain and any offset errors between the plurality of sensed signals due to any inconsistencies between any of the detector devices of the focal plane array and any inconsistencies within the cells of the focal plane array processor itself, and outputs a plurality of processed signals. The sensor also includes a display processor that receives the plurality of processed signals and converts the plurality of processed signals into a video signal suitable for display. The focal plane array processor, the display processor and a controller also provide temperature stabilization of the sensor, manual or automatic calibration of the sensor, manual or automatic gain and level control of the sensor and automatic or manual calibration of the sensor.
Abstract:
An algorithmic approaches that can be implemented in software/firmware/hardware that filters out stable PRI patterns detected within a system that is prosecuting against radar based transmissions are disclosed. The algorithms allow downstream computing assets to concentrate their limited resources on the more complex emitter PRI pattern types. Thus, a portion (e.g., stable signals) of the pulse deinterleave and PRI identification problem is solved without requiring the more computationally expensive processing. The disclosed algorithms can be employed, for example, in electronic support measures (ESM) systems, electronic intelligence (ELINT) systems, and/or a electronic countermeasures (ECM) systems. The algorithms employ linear detection, linear regression, or a combination of linear detection and linear regression, thereby providing a “dual voting” scheme that decreases the occurrence of false positives. Other algorithmic approaches can be used as well in a multi-voting scheme that considers PRI estimates from distinct analysis types.
Abstract:
Pulse integration is utilized on board an optically guided missile or other ordinance device used as a part of a target designation system for extending the lock-on range of the missile by approximately 18%, when a double pulse laser is utilized to illuminate and designate the target. Pulse integration is accomplished with a recirculating delay unit which superimposes the first pulse on the second pulse, such that while the pulses add coherently, noise does not add in phase. The pulse integration technique therefore enhances the signal-to-noise ratio when the missile is at the outer limits of its operating range. When the missile is sufficiently close to the target, doublet decoding is actuated to offer countermeasure resistance. At this point, pulse integration may proceed in lieu of doublet decoding or may be dispensed with in view of the increased signal-to-noise ratio due to the close range of the missile to the target.