公开(公告)号：US20200342918A1

公开(公告)日：2020-10-29

申请号：US16393050

申请日：2019-04-24

申请人： GLOBALFOUNDRIES INC. ,  MARVELL INTERNATIONAL LTD

发明人： Venkatraghavan Bringivijayaraghavan ,  Anoop Delampady ,  Puneet Suri

IPC分类号： G11C7/06 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/08

摘要： Disclosed is a skewed sense amplifier with data and reference sides. The data side has two or more series connected n-type field effect transistors (NFETs) between a data input/output node and a switch to a ground. The reference side has one or more series connected NFETs (but fewer than on the data side) between a reference input/output node and the switch. The data input/output node controls the NFET(s) on the reference side and vice versa. Due to a faster current flow rate through the reference side NFET(s) as compared to the data side NFETs, this amplifier is particularly suited for detecting when, at the initiation of a sensing process, the reference input/output node has a high voltage state and the data input/output node has either a high voltage state or a discharging voltage state. Also disclosed is a memory circuit that incorporates such amplifiers for single-ended read operations.

公开(公告)号：US10818807B2

公开(公告)日：2020-10-27

申请号：US16253191

申请日：2019-01-21

申请人： GLOBALFOUNDRIES INC.

发明人： Ajey Poovannummoottil Jacob ,  Theodore J. Letavic ,  Abu Thomas ,  Yusheng Bian

IPC分类号： H01L31/02 ,  H01L31/18 ,  G02B1/11 ,  G02B5/08 ,  H01L31/0232 ,  H01L31/0216 ,  G02B1/113

摘要： The present disclosure generally relates to semiconductor detectors for use in optoelectronic devices and integrated circuit (IC) chips, and methods for forming same. More particularly, the present disclosure relates to integration of semiconductor detectors with Bragg reflectors. The photodetector of the present disclosure includes a substrate, a Bragg reflector disposed on the substrate, and a semiconductor detector disposed on the Bragg reflector. The Bragg reflector includes alternating layers of a semiconductor material and a dielectric material.

公开(公告)号：US10818803B1

公开(公告)日：2020-10-27

申请号：US16516623

申请日：2019-07-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ali Razavieh

IPC分类号： H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/16

摘要： Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.

公开(公告)号：US10818764B2

公开(公告)日：2020-10-27

申请号：US16520670

申请日：2019-07-24

申请人： GLOBALFOUNDRIES INC.

发明人： John J. Ellis-Monaghan

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

摘要： The present disclosure relates to semiconductor structures and, more particularly, to poly gate extension source to body contact structures and methods of manufacture. The structure includes: a substrate having a doped region; a gate structure over the doped region, the gate structure having a main body and a gate extension region; and a body contact region straddling over the gate extension region and remote from the main body of the gate structure.

公开(公告)号：US10818498B1

公开(公告)日：2020-10-27

申请号：US16407744

申请日：2019-05-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Yanping Shen ,  Haiting Wang ,  Hui Zang

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L29/417 ,  H01L21/768

摘要： Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US10816727B1

公开(公告)日：2020-10-27

申请号：US16441678

申请日：2019-06-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC分类号： G02B6/125 ,  G02B6/136 ,  G02B6/12

摘要： Structures for a waveguide bend and methods of fabricating a structure for a waveguide bend. A waveguide core has a first section, a second section, and a waveguide bend connecting the first section with the second section. The waveguide core includes a first side surface and a second side surface, the first side surface extends about an inner radius of the waveguide bend, and the second side surface extends about an outer radius of the waveguide bend. The waveguide bend includes a central region and a side region that is arranged adjacent to the central region at the first side surface or the second side surface. The central region has a first thickness, and the side region has a second thickness that is less than the first thickness.

公开(公告)号：US20200334014A1

公开(公告)日：2020-10-22

申请号：US16921603

申请日：2020-07-06

申请人： Ranjan B. LOKAPPA ,  Igor ARSOVSKI

发明人： Ranjan B. LOKAPPA ,  Igor ARSOVSKI

IPC分类号： G06F7/506

摘要： An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

公开(公告)号：US10804398B2

公开(公告)日：2020-10-13

申请号：US16160701

申请日：2018-10-15

申请人： GLOBALFOUNDRIES Inc.

发明人： Julien Frougier ,  Ruilong Xie

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

摘要： A device including source-drain epitaxy contacts with a trench silicide (TS) liner wrapped around the source-drain contacts, and method of production thereof. Embodiments include a device having a gate structure formed over a substrate; source-drain epitaxy contacts including a trench silicide (TS) liner covering the source-drain epitaxy contacts; TS contacts formed on the TS liner over the source-drain epitaxy contacts; and a dielectric pillar disposed in a TS cut between the source-drain epitaxy contacts. The TS liner wraps around the source-drain epitaxy contacts, including bottom negatively tapered surfaces of the source-drain epitaxy contacts.

公开(公告)号：US10797138B2

公开(公告)日：2020-10-06

申请号：US15947991

申请日：2018-04-09

申请人： GLOBALFOUNDRIES Inc.

发明人： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC分类号： H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

摘要： Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US10797046B1

公开(公告)日：2020-10-06

申请号：US16369788

申请日：2019-03-29

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Hui Zang

IPC分类号： H01L27/07 ,  H01L49/02 ,  H01L29/78 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L27/02 ,  H01L27/06

摘要： Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material.