公开(公告)号：US20240347652A1

公开(公告)日：2024-10-17

申请号：US18134100

申请日：2023-04-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Yusheng Bian ,  Judson R. Holt

IPC: H01L31/0232 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L31/022408 ,  H01L31/1808

Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a semiconductor layer comprising a crystalline semiconductor material, a waveguide core including a first sidewall and a second sidewall, and a photodetector including a light-absorbing layer, an anode, and a cathode. The light-absorbing layer includes a first portion and a second portion that are disposed on the semiconductor layer. The first portion of the light-absorbing layer is adjacent to the first sidewall of the waveguide core, and the second portion of the light-absorbing layer is adjacent to the second sidewall of the waveguide core.

公开(公告)号：US12111495B2

公开(公告)日：2024-10-08

申请号：US17828139

申请日：2022-05-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/1228 ,  G02B6/12004 ,  G02B6/305 ,  G02B2006/12097 ,  G02B2006/12111 ,  G02B2006/12121 ,  G02B2006/12147

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. The structure comprises an edge coupler including a first waveguide core and a second waveguide core adjacent to the first waveguide core in a lateral direction. The first waveguide core includes a first section with a first thickness and a first plurality of segments projecting in a vertical direction from the first section. The second waveguide core includes a second section with a second thickness and a second plurality of segments projecting in the vertical direction from the second section.

公开(公告)号：US20240329299A1

公开(公告)日：2024-10-03

申请号：US18126745

申请日：2023-03-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125

CPC classification number: G02B6/12004 ,  G02B6/1228 ,  G02B6/125 ,  G02B2006/12104 ,  G02B2006/12121

Abstract: Structures for an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate, a first waveguide core including a curved section and an end that terminates the curved section, and a second waveguide core including a section disposed adjacent to the curved section of the first waveguide core. The first waveguide core is positioned between the second waveguide core and the semiconductor substrate.

公开(公告)号：US20240313054A1

公开(公告)日：2024-09-19

申请号：US18183468

申请日：2023-03-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jianwei PENG ,  Hong Yu

IPC: H01L29/08 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41783 ,  H01L29/42364 ,  H01L29/6656 ,  H01L21/31144

Abstract: An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.

公开(公告)号：US12087384B2

公开(公告)日：2024-09-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming Yin ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

公开(公告)号：US12076692B1

公开(公告)日：2024-09-03

申请号：US18533316

申请日：2023-12-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Justin M. Weinstein

IPC: B01D53/90 ,  B01D53/86

CPC classification number: B01D53/90 ,  B01D53/8696 ,  B01D2251/102 ,  B01D2251/11 ,  B01D2257/2025 ,  B01D2257/2027 ,  B01D2257/2042 ,  B01D2257/2045 ,  B01D2257/2047 ,  B01D2257/406 ,  B01D2257/553 ,  B01D2257/556 ,  B01D2258/0216

Abstract: A system to abate an emission from a first semiconductor process is disclosed. The system includes an abatement apparatus, such as a gas scrubber, to remove hazardous and toxic gas species from the emission. The abatement apparatus may combust the emission to remove these gas species using a fuel and oxidant. The system includes a fuel assembly fluidly coupled to the abatement apparatus which transmits the fuel from at least one source through the abatement apparatus. The fuel assembly may include a supply tank which contains a volume of fuel, a recovery apparatus which recovers and contains a recovery volume of fuel from a second semiconductor process, and a mass flow controller which may transmit fuel from at least one of the supply tank and the recovery apparatus through the abatement apparatus.

公开(公告)号：US20240290879A1

公开(公告)日：2024-08-29

申请号：US18114313

申请日：2023-02-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert ,  James A. Cooper ,  Hema Lata Rao Maddi

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/40 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L21/02337 ,  H01L29/401 ,  H01L29/511 ,  H01L29/517

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.

公开(公告)号：US20240275282A1

公开(公告)日：2024-08-15

申请号：US18166576

申请日：2023-02-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. TRAN ,  Shivraj G. Dharne ,  Asif Iqbal

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/096 ,  H02M1/36

CPC classification number: H02M3/158 ,  H02M1/0009 ,  H02M1/096 ,  H02M1/36

Abstract: A reference circuit for an electronic device having a plurality of power supply voltages comprises a supply start-up circuit, a power-down start-up circuit, and a reference generating circuit. The supply start-up circuit comprising a resistive-capacitive (RC) circuit coupled between a first power supply voltage and a ground. The RC circuit includes a pulse node coupled between a first capacitor and a resistive element, and generates a power-up pulse signal at the pulse node. The power-down start-up circuit is powered by a second power supply voltage and comprises a pulse generation circuit that generates a first start-up signal. The reference generating circuit outputs a reference signal. The reference generating circuit exists a low-power mode when either of the power-up pulse signal and the first start-up signal is generated.

公开(公告)号：US20240274712A1

公开(公告)日：2024-08-15

申请号：US18109126

申请日：2023-02-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/1608 ,  H01L29/66734

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a first doped region, a second doped region, a third doped region, and a trench that includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall. The first doped region is disposed adjacent to the first sidewall of the trench, the second doped region is disposed adjacent to the second sidewall of the trench, the third doped region is disposed adjacent to the trench bottom of the trench. The third doped region connects the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a conductivity type. The structure further comprises a gate structure in the trench.

公开(公告)号：US20240274161A1

公开(公告)日：2024-08-15

申请号：US18166544

申请日：2023-02-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Navneet K. Jain

IPC: G11C5/14 ,  G01R19/165

CPC classification number: G11C5/147 ,  G01R19/16519

Abstract: Embodiments of the disclosure provide a structure and method to ground a reference voltage generator based on a detected supply voltage. A circuit structure according to the disclosure includes a pass gate. The pass gate includes a pair of transistors each coupled to an input signal. One of the pair of transistors of the pass gate includes a gate coupled to a static reference voltage. An inverter couples an output from the pass gate to a device node. The inverter includes a drain terminal, a gate terminal, and a back-gate terminal coupled to ground.