Abstract:
A method, apparatus, and system for determining a horizontal resolution and a phase of an analog video signal arranged to display a number of scan lines each formed of a number of pixels is described. A number of initialization values are set where at least one of the initialization values is a current horizontal resolution and then a difference value for each immediately adjacent ones of the pixels is determined. Next, an edge flag value based upon the difference value is stored in at least one of a number of accumulators such that when at least one of the accumulators has a stored edge flag value that is substantially greater than those stored edge flag values in the other accumulators, then the horizontal resolution is set to the current resolution.
Abstract:
In a digital display device, a packet based method of driving selected pixel elements by way of associated data latches included in a column driver is disclosed. For each frame lines in a video frame, a number of video data packets are provided directly to the column driver at a link rate and each of the number of data latches are populated with appropriate video data based upon video data packets within a line period τ. Selected pixel elements are driven based upon the video data.
Abstract:
A method and an apparatus for performing the method of decoding and playing in reverse MPEG encoded content. The MPEG encoded content comprises a plurality of pictures frames. The picture frames are comprised of one or more picture frame types selected from the group of picture frame types including I-frames, P-frames, and B-frames. The method and the apparatus for performing the method comprise the steps of obtaining a group of MPEG picture frames (“GOP”), determining the total number of picture frames in the GOP, and setting an index value equal to the total number of picture frames in the GOP. Next, a picture frame F that has a display order equal to the index value is decoded and displayed, and the earliest B-frame that depends upon frame F is determined. All the B-frames that depend upon frame F are decoded and displayed from highest display order to lowest display order, and the index value then is set to a value equal to one less than the display order of the earliest B-frame that depends upon frame F. The process then repeats by obtaining, decoding and displaying the next frame F having a display order equal to the index value, and decoding and displaying the B-frames that depend upon the frame F.
Abstract:
Keys (e.g., decryption key, authentication key) are stored in a non-volatile memory of a display unit. The keys are retrieved in encrypted form into an integrated circuit. The integrated circuit decrypts the keys and uses the keys. As the keys are available in decrypted form only within the integrated circuit and potentially only during use, the keys may not be available to unauthorized third parties.
Abstract:
A packet based display interface arranged to couple a multimedia source device to a multimedia sink device is disclosed that includes a transmitter unit coupled to the source device arranged to receive a source packet data stream in accordance with a native stream rate, a receiver unit coupled to the sink device, and a linking unit coupling the transmitter unit and the receiver unit arranged to transfer a multimedia data packet stream formed of a number of multimedia data packets based upon the source packet data stream in accordance with a link rate between the transmitter unit and the receiver unit.
Abstract:
A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. A group of transfer parameters as queue entries allow code and data for an algorithm to be transferred between both local and external memory.
Abstract:
A general method is provided to achieve frequency conversion in an all-digital frequency conversion device that produces an output signal having a selectable phase and frequency that is substantially synchronous with the input signal to be converted. A multiplicity of time-shifted signals is generated, and appropriate ones are selected to set and reset an output signal. An apparatus, computing system, and software product that implement the present invention are also provided.
Abstract:
A method of generating an upsampled target pixel positioned between two lines of input source data includes the step of comparing pixels of different lines of the source data in a region surrounding the upsampled target pixel to be generated in at least two different directions. An interpolation direction based on the comparison is selected and interpolations between selected pixels of the source data in the determined interpolation direction are carried out to compute intermediate pixels on a line segment passing through the upsampled target pixel. An interpolation between the intermediate pixels is carried out to generate the upsampled target pixel. An apparatus for performing the method is also disclosed.
Abstract:
The invention provides for automatically identifying the location of a displayed video window based upon a characterization of selected portions of the image for realness based upon a distribution of luminance values for the selected portions. The image is then searched mathematically for a large rectangle of realness, and if found, a similar operation is performed in a smaller rectangle around each of the edges of the large rectangle, in turn, zooming in to a resolution of one pixel, thus identifying the position of the edge. This process can be repeated as often as necessary in order to maintain a fix on the edges of the video window.
Abstract:
A display controller coupled to a display device by way of a display interface and to a host device by way of a data port that includes a processor arranged to process executable instructions and associated data, a single memory device for storing the executable instructions and associated data and EDID corresponding to the display device, and a bridge portion coupling the single memory device to the host device by way of the data port, wherein the bridge portion is always in a powered on state thereby providing access to the single memory device by the host device even when the display controller is in a powered off state such as during a boot up process when the display controller is in the powered off state.