-
公开(公告)号：US20240161343A1
公开(公告)日：2024-05-16
申请号：US18331166
申请日：2023-06-07
发明人： Yi-Hsuan HUANG , Yao-Jia KUO , Yu-Chi TSAI , Wen-Tsung HUANG
CPC分类号： G06T7/80 , G06T5/003 , G06T5/006 , G06T5/50 , G06T7/11 , G06T7/13 , G06T2207/10016 , G06T2207/10024 , G06T2207/20132
摘要： An image processing method includes following operations: receiving, by a processor, an input image from a camera; performing, by the processor, a top-view calibration process to generate a top-view calibrated image according to the input image; performing, by the processor, an object extraction process on the top-view calibrated image to generate at least one target object frame; performing, by the processer, a centering process on the at least one target object frame to generate a centered image; and outputting, by the processor, the centered image for a display panel to display.
-
公开(公告)号：US20240159826A1
公开(公告)日：2024-05-16
申请号：US18388545
申请日：2023-11-10
发明人： CHUNG-YI WANG , CHIA-CHE WU
IPC分类号： G01R31/317
CPC分类号： G01R31/31718
摘要： An automated test mechanism includes: preparing test software capable of reading and processing a file in a general form, and making the test software support N kinds of communication interfaces, M kinds of communication protocols, and multiple commands of K kinds of instruments, wherein the general form includes an interface setting part, a communication protocol setting part, and a function list part; creating multiple general form files in the general form to support the K kinds of instruments, wherein the multiple general form files include a first file and a second file that are prepared for a first instrument and a second instrument of the multiple instruments respectively; and when performing a first test with the first instrument, choosing the first file for the first test, and when performing a second test with the second instrument, choosing the second file for the second test.
-
公开(公告)号：US20240135999A1
公开(公告)日：2024-04-25
申请号：US17973005
申请日：2022-10-24
发明人： FU-CHIN TSAI , GER-CHIH CHOU , CHUN-CHI YU , CHIH-WEI CHANG
摘要： The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.
-
公开(公告)号：US11966531B2
公开(公告)日：2024-04-23
申请号：US18197750
申请日：2023-05-16
发明人： Hsu-Ming Tsai
CPC分类号： G06F3/0416 , G06F3/044 , G06F3/0418 , G06F2203/04107 , G06F2218/04
摘要： A capacitive sensing device includes a switch circuitry, a counter circuit, a comparator circuit, an amplifier circuit including first and second input terminals and an output terminal, and a feedback capacitor coupled between the output terminal and the first input terminal. The switch circuitry transmits a reference voltage to the second input terminal and couples the first input terminal to the output terminal during a first phase, transmits another reference voltage to the second input terminal during a second phase, and adjusts a voltage of the output terminal during a third phase. The counter circuit starts counting and the comparator circuit generates the control signal according to the output voltage and the second reference voltage during the third phase. The counter circuit stops counting according to the control signal to generate a count value indicating a capacitance value change of a capacitor under-test coupled to the first input terminal.
-
公开(公告)号：US11955976B2
公开(公告)日：2024-04-09
申请号：US17973706
申请日：2022-10-26
发明人： Yao-Chia Liu , Yuan-Sheng Lee
IPC分类号： H03K5/00 , H03K5/131 , H03K5/135 , H03K5/15 , H03K19/173
CPC分类号： H03K5/135 , H03K5/131 , H03K5/15093 , H03K19/1737
摘要： A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.
-
公开(公告)号：US20240113723A1
公开(公告)日：2024-04-04
申请号：US18129109
申请日：2023-03-31
发明人： SHIH-HSIUNG HUANG
CPC分类号： H03M1/1245 , H03M1/0668
摘要： A time-interleaved analog to digital converter includes first and second capacitor array circuits, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a noise shaping signal conversion on the first and second residues to generate a second quantization signal. A turn-on time of the corresponding first transfer circuit is determined based on the coarse conversion corresponding to a first capacitor array circuit and the noise shaping signal conversion corresponding to a second capacitor array circuit to selectively bring forward a start time of the noise shaping signal conversion. The encoder circuit generates a digital output according to the first and the second quantization signals.
-
37.发明公开公开(公告)号：US20240113720A1
公开(公告)日：2024-04-04
申请号：US18140746
申请日：2023-04-28
发明人： SHIH-HSIUNG HUANG
IPC分类号： H03M1/08
CPC分类号： H03M1/08
摘要： A time-interleaved analog to digital converter (ADC) includes capacitor array circuits, a flash ADC, first and second circuits, a converter, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residue signals according to first quantization signals. The flash ADC samples the input signal and generates the first quantization signals. The first circuits transfer the first residue signals from the capacitor array circuits. The converter performs a signal conversion according to the first and the second residue signals to generate a second quantization signal. The second circuits transfer second residue signals to the converter. The capacitor array circuits further generate the second residue signal in response to the signal conversion. The encoder circuit generates a digital output according to one of the first quantization signals and the second quantization signals.
-
公开(公告)号：US11942258B2
公开(公告)日：2024-03-26
申请号：US17371250
申请日：2021-07-09
发明人： Hsiao-Tsung Yen , Ting-Yao Huang , Ka-Un Chan
CPC分类号： H01F27/2804 , H01F17/0013 , H01F27/2828 , H01F27/29 , H01F2017/004 , H01F2017/0073 , H01F2027/2809
摘要： An inductor device includes a first and a second inductor and a first and a second connection member. A first and a second trace of the first inductor is located on a first and a second layer respectively. The second trace is coupled to the first trace located at a first and a second area. The first connection member is coupled to the second trace. A third and a fourth trace of the second inductor is located on the first and the second layer respectively. The first trace and the third trace are disposed in turn at the first area and the second area. The fourth trace is coupled to the third trace located at the first and the second area. The second and the fourth trace are disposed in turn at the first and the second area. The second connection member is coupled to the fourth trace.
-
公开(公告)号：US11923831B2
公开(公告)日：2024-03-05
申请号：US17828516
申请日：2022-05-31
发明人： Shih-Hsiung Huang
IPC分类号： H03K17/06 , H03K17/0412 , H03K19/017
CPC分类号： H03K17/063 , H03K17/04123 , H03K19/01735
摘要： A bootstrapped switch includes a first transistor, a second transistor, a first capacitor, three switches, and a switch circuit. The switch circuit includes a first switch, a second switch, a second capacitor, and a resistor. The first transistor receives the input voltage and outputs the output voltage. The first terminal of the second transistor receives the input voltage, and the second terminal of the second transistor is coupled to the first terminal of the first capacitor. The control terminal of the first switch receives a clock. The second switch is coupled between the control terminal of the first transistor and the first switch. The second capacitor is coupled between the control terminal of the first switch and the control terminal of the second switch. The resistor is coupled between the control terminal of the second switch and a reference voltage.
-
公开(公告)号：US20240073179A1
公开(公告)日：2024-02-29
申请号：US18452541
申请日：2023-08-20
发明人： YUAN HONG
IPC分类号： H04L61/5007
CPC分类号： H04L61/5007
摘要： A network control method is configured to balance the loading of a plurality of processes. The method includes obtaining an IP address of a packet; deleting a portion of bits of the IP address to generate a series according to an IP address entropy distribution; performing a hash function to the series to generate a hash value; performing a modulo operation to the hash value to obtain a remainder; and assigning the packet to a processor of the plurality of processes corresponding to the remainder.
-
-
-
-
-
-
-
-
-
搜索结果
1667 条记录 (耗时 0.035 秒)
