Self-test circuit, and corresponding device, vehicle and method

    公开(公告)号:US11077755B2

    公开(公告)日:2021-08-03

    申请号:US16420875

    申请日:2019-05-23

    Abstract: A circuit includes a differential stage configured to provide a differential output signal. An analog-to-digital converter is coupled to first and second output nodes of the differential stage. The analog-to-digital converter is configured to provide an output signal that is a function of the differential output signal from the differential stage. A multiplexer is configured to receive a differential input signal. The multiplexer includes a test switch switchable between a conductive state and a non-conductive state. In the conductive state, the test switch couples the first input node and the second input node of the differential stage. Test signal injection circuitry is activatable to force a differential current through the differential stage. The circuit is selectively switchable between an operational mode and a self-test mode.

    METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, SEMICONDUCTOR PRODUCT, DEVICE AND TESTING METHOD

    公开(公告)号:US20210233884A1

    公开(公告)日:2021-07-29

    申请号:US17158781

    申请日:2021-01-26

    Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.

    ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING ELECTRONIC CIRCUITS

    公开(公告)号:US20210232174A1

    公开(公告)日:2021-07-29

    申请号:US17159511

    申请日:2021-01-27

    Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

    HALF-BRIDGE CONTROL CIRCUIT, RELATED INTEGRATED CIRCUIT AND HALF-BRIDGE CIRCUIT

    公开(公告)号:US20210226624A1

    公开(公告)日:2021-07-22

    申请号:US17150156

    申请日:2021-01-15

    Abstract: An embodiment half-bridge control circuit comprises an input terminal, an output terminal for providing a pulsed signal to a half-bridge driver circuit configured to drive two electronic switches connected between two supply terminals, and a feedback terminal for receiving a feedback signal indicative of the instantaneous voltage value at a switching node between the two electronic switches. A selector circuit provides a digital feedback signal. A subtractor generates an error signal by subtracting the digital feedback signal from the reference signal. An integrator generates an integration signal by integrating the value of the error signal. A down-scale circuit generates a reduced resolution integration signal by discarding one or more least significant bits of the integration signal. A sampling circuit generates a sampled integration signal by sampling the reduced resolution integration signal. A pulse generator circuit generates the pulsed signal as a function of the sampled integration signal.

    PFC CONTROL CIRCUIT FOR A BOOST CONVERTER, RELATED INTEGRATED CIRCUIT, BOOST CONVERTER, POWER SUPPLY AND METHOD

    公开(公告)号:US20210226527A1

    公开(公告)日:2021-07-22

    申请号:US17151397

    申请日:2021-01-18

    Abstract: An embodiment PFC control circuit comprises a first terminal providing a drive signal to an electronic switch of a boost converter, a second terminal receiving a feedback signal indicative of an output voltage generated by the boost converter, and a third terminal connected to a compensation network. An error amplifier generates a current as a function of the voltage at the second terminal and a reference voltage, wherein an output of the error amplifier is coupled to the third terminal. A driver circuit generates the drive signal as a function of the voltage at the third terminal, and selectively activates or deactivates the generation of the drive signal as a function of a burst mode enable signal. A detection circuit generates the burst mode enable signal as a function of the voltage at the second terminal.

    COMPUTING SYSTEM IMPLEMENTING AN ALGORITHM FOR FUSING DATA FROM INERTIAL SENSORS, AND METHOD

    公开(公告)号:US20210207940A1

    公开(公告)日:2021-07-08

    申请号:US17207180

    申请日:2021-03-19

    Abstract: A computing system includes a first hardware element having a first accelerometer and a first gyroscope, and a second hardware element having a second accelerometer and a second gyroscope. The first and second hardware elements are moveable with respect to each other. The computing system recursively generates a result signal indicative of a relative orientation of the first and second hardware elements with respect to each other. The result signal may be generated by generating a first intermediate signal indicative of a angle between the first and second hardware elements based on signals generated by the first and second accelerometers and generating a second intermediate signal indicative of the angle based on signals generated by the first and second gyroscopes. The result signal indicative of the angle may be generated as a weighted sum of the first intermediate signal and the second intermediate signal. At least one of the first and second hardware elements is controlled by on the result signal.

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