公开(公告)号：US20220223706A1

公开(公告)日：2022-07-14

申请号：US17163589

申请日：2021-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786

Abstract: A semiconductor device includes a substrate and a first transistor disposed on the substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. A material composition of the first vertical portion is identical to a material composition of each of the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions.

公开(公告)号：US20220222162A1

公开(公告)日：2022-07-14

申请号：US17180897

申请日：2021-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pei LIN ,  Ji-Fu KUNG ,  Te-Hsuan CHEN ,  Yi-Lin HUNG

IPC: G06F11/32 ,  G06F11/34 ,  G06F11/30 ,  G06K9/62

Abstract: An operation method and an operation device of a failure detection and classification (FDC) model are provided. The operation method of the FDC model includes the following steps. A plurality of raw traces are continuously obtained. If the raw traces have started to be changed from the first waveform to the second waveform, whether at least N pieces in the race traces have been changed to the second waveform is determined. If at least N pieces in the raw traces have been changed to the second waveform, the raw traces which have been changed to the second waveform are automatically segmented to obtain several windows. An algorithm is automatically set for each of the windows. Through each of the algorithms, an indicator of each of the windows is obtained. The FDC model is retrained based on these indicators.

公开(公告)号：US11387337B2

公开(公告)日：2022-07-12

申请号：US17134131

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

公开(公告)号：US20220216397A1

公开(公告)日：2022-07-07

申请号：US17705404

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

IPC: H01L43/12 ,  H01L23/544 ,  H01L43/02 ,  H01L27/22

Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

公开(公告)号：US20220216344A1

公开(公告)日：2022-07-07

申请号：US17705376

申请日：2022-03-27

Applicant: United Microelectronics Corp.

Inventor： Su Xing ,  Chung Yi Chiu ,  Hai Biao Yao

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8232 ,  H01L21/225 ,  H01L21/762 ,  H01L29/749

Abstract: A structure of field-effect transistor includes a silicon layer of a silicon-on-insulator structure. A gate structure layer in a line shape is disposed on the silicon layer, wherein the gate structure layer includes a first region and a second region abutting to the first region. Trench isolation structures in the silicon layer are disposed at two sides of the gate structure layer, corresponding to the second region. The second region of the gate structure layer is disposed on the silicon layer and overlaps with the trench isolation structure. A source region and a drain region are disposed in the silicon layer at the two sides of the gate structure layer, corresponding to the first region. The second region of the gate structure layer includes a conductive-type junction portion.

公开(公告)号：US20220216311A1

公开(公告)日：2022-07-07

申请号：US17178269

申请日：2021-02-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Haw Lee ,  Tzu-Ping Chen

IPC: H01L21/28 ,  H01L29/788 ,  H01L29/423 ,  H01L21/311 ,  H01L21/32 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/66

Abstract: A split-gate flash memory cell includes a semiconductor substrate having thereon a select gate oxide layer and a floating gate oxide layer. A floating gate is disposed on the floating gate oxide layer. A football-shaped oxide layer is disposed on the floating gate. The floating gate includes tips under the football-shaped oxide layer. A select gate is disposed on the select gate oxide layer and extended onto the football-shaped oxide layer. An inter-poly oxide layer is between the select gate and the floating gate. The inter-poly oxide layer has a thickness smaller than a thickness of the select gate oxide layer. A source region is formed in the semiconductor substrate and adjacent to the floating gate. A drain region is formed in the semiconductor substrate and adjacent to the select gate.

公开(公告)号：US11381247B1

公开(公告)日：2022-07-05

申请号：US17225074

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hong Hsu ,  Po-Hua Chen ,  Yu-Yee Liow ,  Chih-Wei Wu ,  Hsuan-Chih Yeh

IPC: H03D3/24 ,  H03L7/089 ,  H03L7/10 ,  H03L7/083 ,  H03L7/095

Abstract: An apparatus includes a phase-locked loop and a jitter detection circuit. A method of detecting a jitter in the apparatus includes the phase-locked loop generating a lead control signal and a lag control signal according to a reference clock and a feedback clock, the jitter detection circuit generating a jitter signal according to the lead control signal and the lag control signal, the jitter detection circuit generating a jitter window signal according to the jitter signal, the jitter detection circuit identifying jitters in the clock signal according to the jitter signal and the jitter window signal, and the jitter detection circuit outputting a jitter indication signal according to the number of jitters identified.

公开(公告)号：US11380786B2

公开(公告)日：2022-07-05

申请号：US16519008

申请日：2019-07-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao

IPC: H01L29/778 ,  H01L21/3105 ,  H01L23/31 ,  H01L29/66

Abstract: An insulating structure of a high electron mobility transistor (HEMT) is provided, which comprises a gallium nitride layer, an aluminum gallium nitride layer disposed on the gallium nitride layer, a groove disposed in the gallium nitride layer and the aluminum gallium nitride layer, an insulating layer disposed in the groove, wherein a top surface of the insulating layer is aligned with a top surface of the aluminum gallium nitride layer, and a passivation layer, disposed on the aluminum gallium nitride layer and the insulating layer.

公开(公告)号：US11366604B1

公开(公告)日：2022-06-21

申请号：US17210545

申请日：2021-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Chin Chang ,  Ming-Jen Chang ,  Cheng-Hsiao Lai ,  Yu-Syuan Lin ,  Chi-Fa Lien ,  Ying-Ting Lin ,  Yung-Tsai Hsu

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28 ,  G11C16/22

Abstract: A physically unclonable function includes a flash memory, a current comparator and a controller. The flash memory includes a plurality of memory cells. A method of operating the physically unclonable function circuit includes the controller setting the plurality of memory cells to an initial data state, the controller setting the plurality of memory cells between the initial data state and an adjacent data state of the initial data state, the current comparator reading a first current from a memory cell in a first section of the plurality of the memory cells, the current comparator reading a second current from a memory cell in a second section of the plurality of the memory cells, and the current comparator outputting a random bit according to the first current and the second current.

公开(公告)号：US20220181481A1

公开(公告)日：2022-06-09

申请号：US17140157

申请日：2021-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shou-Wan Huang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; removing part of the first fin-shaped structure to form a first trench; forming a dielectric layer in the first trench to form a double diffusion break (DDB) structure; and forming a first gate structure and a second gate structure on the DDB structure. Preferably, a bottom surface of the first gate structure is lower than a top surface of the first fin-shaped structure.