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    Scheduling memory requests for a ganged memory device
    401.
    发明授权
    Scheduling memory requests for a ganged memory device 有权

    公开(公告)号：US11422707B2

    公开(公告)日：2022-08-23

    申请号：US15851479

    申请日：2017-12-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： James Raymond Magro

    IPC: G06F13/16 ,  G06F9/50 ,  G06F3/06 ,  G06F12/10

    Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.

    Selectively performing ahead branch prediction based on types of branch instructions
    402.
    发明授权
    Selectively performing ahead branch prediction based on types of branch instructions 有权

    公开(公告)号：US11416256B2

    公开(公告)日：2022-08-16

    申请号：US16945275

    申请日：2020-07-31

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Marius Evers ,  Aparna Thyagarajan ,  Ashok T. Venkatachar

    IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/38 ,  G06F9/355 ,  G06F9/35

    Abstract: A set of entries in a branch prediction structure for a set of second blocks are accessed based on a first address of a first block. The set of second blocks correspond to outcomes of one or more first branch instructions in the first block. Speculative prediction of outcomes of second branch instructions in the second blocks is initiated based on the entries in the branch prediction structure. State associated with the speculative prediction is selectively flushed based on types of the branch instructions. In some cases, the branch predictor can be accessed using an address of a previous block or a current block. State associated with the speculative prediction is selectively flushed from the ahead branch prediction, and prediction of outcomes of branch instructions in one of the second blocks is selectively initiated using non-ahead accessing, based on the types of the one or more branch instructions.

    INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP
    405.
    发明申请
    INSET POWER POST AND STRAP ARCHITECTURE WITH REDUCED VOLTAGE DROOP 有权

    公开(公告)号：US20220208678A1

    公开(公告)日：2022-06-30

    申请号：US17135122

    申请日：2020-12-28

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Richard SCHULTZ

    IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/45 ,  H01L21/285 ,  H01L21/8238

    Abstract: A cell layout implemented in an integrated circuit (IC) includes a first plurality of independent power posts in a first metal layer. Each independent power post of the plurality of independent power posts provides a power connection to one device of a plurality of devices within the cell layout. A source or drain of each device of the plurality of devices is connected to one independent power post of the plurality of independent power posts. The IC further includes a plurality of independent power straps in a second metal layer that is different from the first metal layer. Each independent power strap of the plurality of independent power straps spans across and connects to multiple independent power posts of the first plurality of independent power posts.

    HIGH-SPEED DIE CONNECTIONS USING A CONDUCTIVE INSERT
    409.
    发明申请
    HIGH-SPEED DIE CONNECTIONS USING A CONDUCTIVE INSERT 有权

    公开(公告)号：US20220189897A1

    公开(公告)日：2022-06-16

    申请号：US17118126

    申请日：2020-12-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： RAHUL AGARWAL

    IPC: H01L23/00 ,  H01L23/528

    Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

    THROTTLING HULL SHADERS BASED ON TESSELLATION FACTORS IN A GRAPHICS PIPELINE
    410.
    发明申请
    THROTTLING HULL SHADERS BASED ON TESSELLATION FACTORS IN A GRAPHICS PIPELINE 有权

    公开(公告)号：US20220189112A1

    公开(公告)日：2022-06-16

    申请号：US17121965

    申请日：2020-12-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Nishank PATHAK

    IPC: G06T17/20 ,  G06T15/00

    Abstract: A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.

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