公开(公告)号：US20220013531A1

公开(公告)日：2022-01-13

申请号：US17179057

申请日：2021-02-18

Applicant: Silicon Storage Technology, Inc.

Inventor： Jeng-Wei YANG ,  Man-Tang WU ,  Boolean FAN ,  Nhan DO

IPC: H01L27/11524 ,  G11C16/04 ,  H01L29/66

Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

公开(公告)号：US11205490B2

公开(公告)日：2021-12-21

申请号：US16828206

申请日：2020-03-24

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/16 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11524 ,  G11C16/28 ,  G11C29/50 ,  G11C16/34 ,  G11C29/04 ,  G11C29/44

Abstract: A memory device that includes a plurality of non-volatile memory cells and a controller. The controller is configured to erase the plurality of memory cells, program each of the memory cells, and for each of the memory cells, measure a threshold voltage applied to the memory cell corresponding to a target current through the memory cell in a first read operation, re-measure a threshold voltage applied to the memory cell corresponding to the target current through the memory cell in a second read operation, and identify the memory cell as defective if a difference between the measured threshold voltage and the re-measured threshold voltage exceeds a predetermined amount.

公开(公告)号：US11188237B2

公开(公告)日：2021-11-30

申请号：US16228313

申请日：2018-12-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Nhan Do

IPC: G06F3/06 ,  G11C16/28 ,  G11C7/06 ,  G11C29/48 ,  G11C29/02 ,  G11C29/18 ,  G06F11/07 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L21/78 ,  H01L27/11521 ,  H01L29/423 ,  G11C29/04 ,  G11C29/12 ,  G11C29/44 ,  H01L23/00

Abstract: Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

公开(公告)号：US20210334639A1

公开(公告)日：2021-10-28

申请号：US17367542

申请日：2021-07-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06N3/063 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for programmable output blocks for use with a VMM array within an artificial neural network. In one embodiment, the gain of an output block can be configured by a configuration signal. In another embodiment, the resolution of an ADC in the output block can be configured by a configuration signal.

公开(公告)号：US20210327512A1

公开(公告)日：2021-10-21

申请号：US17074103

申请日：2020-10-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo XING ,  Chunming WANG ,  Xian LIU ,  Nhan DO ,  Guangming LIN ,  Yaohua ZHU

IPC: G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: The present invention relates to a flash memory device that uses strap cells in a memory array of non-volatile memory cells as source line pull down circuits. In one embodiment, the strap cells are erase gate strap cells. In another embodiment, the strap cells are source line strap cells. In another embodiment, the strap cells are control gate strap cells. In another embodiment, the strap cells are word line strap cells.

公开(公告)号：US20210264983A1

公开(公告)日：2021-08-26

申请号：US16985147

申请日：2020-08-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Steven Lemke ,  Hieu Van Tran ,  Yuri Tkachev ,  Louisa Schneider ,  Henry A. Om'Mani ,  Thuan Vu ,  Nhan Do ,  Vipin Tiwari

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G06N3/063

Abstract: Embodiments for ultra-precise tuning of a selected memory cell are disclosed. The selected memory cell optionally is first programmed using coarse programming and fine programming methods. The selected memory cell then undergoes ultra-precise programming through the programming of an adjacent memory cell. As the adjacent memory cell is programmed, capacitive coupling between the floating gate of the adjacent memory cell and the floating gate of the selected memory cell will cause the voltage of the floating gate of the selected memory cell to increase, but in smaller increments than could be achieved by programming the selected memory cell directly. In this manner, the selected memory cell can be programmed with ultra-precise gradations.

公开(公告)号：US20210241839A1

公开(公告)日：2021-08-05

申请号：US17239397

申请日：2021-04-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US11017866B2

公开(公告)日：2021-05-25

申请号：US16803401

申请日：2020-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/24 ,  G11C16/26 ,  G11C16/16 ,  H01L27/11529 ,  H01L27/11524

Abstract: A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state. The method includes testing the memory cells to confirm the memory cells are operational, programming each of the memory cells to a mid-program state, and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state. Each memory cell has a first threshold voltage when programmed in the minimum program state, a second threshold voltage when programmed in the maximum program state, and a third threshold voltage when programmed in the mid-program state. The third threshold voltage is substantially at a mid-point between the first and second threshold voltages, and corresponds to a substantially logarithmic mid-point of read currents.

公开(公告)号：US20210142156A1

公开(公告)日：2021-05-13

申请号：US16751202

申请日：2020-01-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G06N3/04 ,  G06F17/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20210098477A1

公开(公告)日：2021-04-01

申请号：US17121555

申请日：2020-12-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  VIPIN TIWARI ,  NHAN DO ,  MARK REITEN

IPC: H01L27/11531 ,  G06N3/08 ,  G11C16/04 ,  H01L29/788

Abstract: Numerous embodiments for reading a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input pulses applied to a terminal of the selected memory cell, further resulting in a series of output signals that are summed to determine the value stored in the selected memory cell. In another embodiment, an input comprises a set of input bits, where each input bit results in a single pulse or no pulse being applied to a terminal of the selected memory cell, further resulting in a series of output signals which are then weighted according to the binary bit location of the input bit, and where the weighted signals are then summed to determine the value stored in the selected memory cell.