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公开(公告)号：US20210065817A1
公开(公告)日：2021-03-04
申请号：US16803401
申请日：2020-02-27
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
IPC: G11C16/26 , H01L27/11524 , H01L27/11529 , G11C16/16
Abstract: A method of improving stability of a memory device having a controller configured to program each of a plurality of non-volatile memory cells within a range of programming states bounded by a minimum program state and a maximum program state. The method includes testing the memory cells to confirm the memory cells are operational, programming each of the memory cells to a mid-program state, and baking the memory device at a high temperature while the memory cells are programmed to the mid-program state. Each memory cell has a first threshold voltage when programmed in the minimum program state, a second threshold voltage when programmed in the maximum program state, and a third threshold voltage when programmed in the mid-program state. The third threshold voltage is substantially at a mid-point between the first and second threshold voltages, and corresponds to a substantially logarithmic mid-point of read currents.
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公开(公告)号：US20210407602A1
公开(公告)日：2021-12-30
申请号：US16915289
申请日：2020-06-29
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
Abstract: A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.
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公开(公告)号：US20200065023A1
公开(公告)日：2020-02-27
申请号：US16217916
申请日：2018-12-12
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
IPC: G06F3/06
Abstract: A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region. Control circuitry is configured to, for one of the memory cells, apply a first pulse of programming voltages that includes a first voltage applied to the control gate, perform a read operation that includes detecting currents through the channel region for different control gate voltages to determine a target control gate voltage using the detected currents that corresponds to a target current through the channel region, and apply a second pulse of programming voltages that includes a second voltage applied to the control gate that is determined from the first voltage, a nominal read voltage and the target voltage.
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公开(公告)号：US12014793B2
公开(公告)日：2024-06-18
申请号：US17858185
申请日：2022-07-06
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
CPC classification number: G11C29/50016 , G11C16/14 , G11C16/26 , G11C16/349 , G11C29/50004 , G11C2029/5004 , G11C2029/5006
Abstract: A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.
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公开(公告)号：US20230335212A1
公开(公告)日：2023-10-19
申请号：US17858185
申请日：2022-07-06
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , ALEXANDER KOTOV
CPC classification number: G11C29/50016 , G11C16/14 , G11C16/26 , G11C16/349 , G11C29/50004 , G11C2029/5006 , G11C2029/5004
Abstract: A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.
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Patent Agency Ranking
公开(公告)号：US11309042B2
公开(公告)日：2022-04-19
申请号：US16915289
申请日：2020-06-29
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
Abstract: A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.
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公开(公告)号：US10991433B2
公开(公告)日：2021-04-27
申请号：US16803418
申请日：2020-02-27
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
Abstract: A memory device having non-volatile memory cells and a controller. In response to a first command for erasing and programming a first group of the memory cells, the controller determines the first group can be programmed within substantially 10 seconds of their erasure, erases the first group, and programs the first group within substantially 10 seconds of their erasure. In response to a second command for erasing and programming a second group of the memory cells, the controller determines that the second group cannot be programmed within substantially 10 seconds of their erasure, divides the second group into subgroups of the memory cells each of which can be programmed within substantially 10 seconds of their erasure, and for each of the subgroups, erase the subgroup and program the subgroup within substantially 10 seconds of their erasure.
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8.发明申请System And Method For Programming Split-Gate, Non-volatile Memory Cells 审中-公开用于编程分离门，非易失性存储单元的系统和方法公开(公告)号：US20160336072A1
公开(公告)日：2016-11-17
申请号：US15084955
申请日：2016-03-30
Applicant: Silicon Storage Technology, Inc.
Inventor： Xiaozhou Qian , Viktor Markov , Jong-Won Yoo , Xiao Yan Pi , Alexander Kotov
CPC classification number: G11C16/12 , G11C16/0425 , G11C16/10
Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.
Abstract translation: 所公开的实施例包括闪存器件和以与现有技术方法相比降低器件劣化的方式对器件进行编程的方法。
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公开(公告)号：US12080355B2
公开(公告)日：2024-09-03
申请号：US17481225
申请日：2021-09-21
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
CPC classification number: G11C16/26 , G11C16/0425 , G11C16/14 , G11C16/3431
Abstract: A memory device and method for a non-volatile memory cell having a gate that includes programming the memory cell to an initial program state corresponding to a target read current and a threshold voltage, including applying a program voltage having a first value to the gate, storing the first value in a memory, reading the memory cell in a first read operation using a read voltage applied to the gate that is less than the target threshold voltage to generate a first read current, and subjecting the memory cell to additional programming in response to determining that the first read current is greater than the target read current. The additional programming includes retrieving the first value from the memory, determining a second value greater than the first value, and programming the selected non-volatile memory cell that includes applying a program voltage having the second value to the gate.
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10.发明授权公开(公告)号：US11769558B2
公开(公告)日：2023-09-26
申请号：US17482095
申请日：2021-09-22
Applicant: Silicon Storage Technology, Inc.
Inventor： Viktor Markov , Alexander Kotov
CPC classification number: G11C16/3427 , G11C16/10 , G11C16/14 , G11C16/26 , G11C2216/04
Abstract: A method of programing a memory device having a plurality of memory cell groups where each of the memory cell group includes N non-volatile memory cells, where N is an integer greater than or equal to 2. For each memory cell group, the method includes programming each of the non-volatile memory cells in the memory cell group to a particular program state, performing multiple read operations on each of the non-volatile memory cells in the memory cell group, identifying one of the non-volatile memory cells in the memory cell group that exhibits a lowest read variance during the multiple read operations, deeply programming all of the non-volatile memory cells in the memory cell group except the identified non-volatile memory cell, and programming the identified non-volatile memory cell in the memory cell group with user data.
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