公开(公告)号：US20030231538A1

公开(公告)日：2003-12-18

申请号：US10331135

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Danilo Rimondi ,  Cosimo Torelli

IPC: G11C007/00

CPC classification number: G11C7/20 ,  G11C11/419

Abstract: A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies, respectively. The cell also comprises means, responsive to a memory cell selection signal, for selectively connecting an input of at least one of the first and second inverter to at least one respective input/output data line, carrying an input datum to be written in the memory cell in a memory cell write operation and an output datum read from the memory cell in a memory cell read operation. For-flash-clearing the memory cell, means are provided for switching at least one of the first and second voltage supply receiving means of at least one of the first and second inverters between the first voltage supply and the second voltage supply. The memory cell is particularly adapted to implement a flash-clear function in a memory device.

Abstract translation: 存储单元包括以锁存配置连接的第一和第二反相器。 逆变器具有分别用于接收第一和第二电压源的相应的第一和第二装置。 单元还包括响应于存储器单元选择信号的装置，用于将第一和第二反相器中的至少一个的输入选择性地连接到至少一个相应的输入/输出数据线，承载要写入存储器的输入数据 在存储单元读取操作中存储单元写入操作和从存储器单元读取的输出数据。 为了闪存清除存储单元，提供了用于在第一电压源和第二电压源之间切换第一和第二逆变器中的至少一个的第一和第二电压供应接收装置中的至少一个的装置。 存储器单元特别适于在存储器件中实现闪光功能。

公开(公告)号：US20030174531A1

公开(公告)日：2003-09-18

申请号：US10360840

申请日：2003-02-07

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: G11C011/22

CPC classification number: G11C11/005

Abstract: An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.

Abstract translation: 一种集成装置，包括具有非易失型第一存储单元的第一存储器阵列和具有易失型（DRAM）的第二存储单元的第二存储器阵列。 第一存储单元和第二存储单元形成在半导体材料的衬底中，并且每个包括形成在衬底的有源区中的各自的MOS晶体管，并且具有形成在顶部的第一导电区域和相应的电容器 并且具有由电介质区域分离的第一电极和第二电极。 此外，电容器的第一电极连接到MOS晶体管的第一导电区域。 第一和第二存储单元具有基本上相同并且同时形成的结构。

公开(公告)号：US20030174010A1

公开(公告)日：2003-09-18

申请号：US10371151

申请日：2003-02-21

Applicant: STMicroelectronics S.r.I.

Inventor： Domenico Pappalardo ,  Maurizio Gaibotti

IPC: G05F001/10

CPC classification number: H02M3/073

Abstract: The charge pump uses PMOS transistors for implementing the first and the second charge transfer switches of the charge pump. Substantially, the closing and opening of the first switch through which the first capacitor is charged, of the second switch for transferring the electric charge from the first capacitor to the load capacitance connected to the output node of the circuit and of the third switch for discharging to ground the load capacitance, are driven by a logic NOR gate. A first input of the NOR gate is connected to a common control node of the PMOS transistor forming the second switch and of a NMOS transistor forming the third switch, a second inverting input is connected to the output node, and the output is connected to the first capacitor.

Abstract translation: 电荷泵使用PMOS晶体管来实现电荷泵的第一和第二电荷转移开关。 基本上，将第一电容器充电的第一开关的闭合和打开用于将电荷从第一电容器转移到连接到电路的输出节点的负载电容的第二开关和用于放电的第三开关 接地负载电容，由逻辑或非门驱动。 NOR门的第一输入端连接到形成第二开关的PMOS晶体管和形成第三开关的NMOS晶体管的公共控制节点，第二反相输入端连接到输出节点，输出端连接到 第一个电容。

公开(公告)号：US20030151949A1

公开(公告)日：2003-08-14

申请号：US10331116

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Sabina Mognoni ,  Ilaria Motta ,  Andrea Sacco

IPC: G11C011/34

CPC classification number: G11C16/30

Abstract: A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

Abstract translation: 一种方法和程序加载电路用于调节正被编程的非易失性存储单元的漏极和体端子处的电压。 这些电压从连接在导通图案中的编程负载电路施加，以将预定的电压值传送到存储单元的至少一个端子。 该方法包括在编程负载电路内局部调节电压值以克服存在于导电图案中的寄生电阻的影响的步骤。

公开(公告)号：US20030142568A1

公开(公告)日：2003-07-31

申请号：US10331147

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Giove ,  Luca De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiulo ,  Kumar Promod ,  Giuseppe Piazza ,  Francesco Pipitone

IPC: G11C007/02 ,  G11C007/00

CPC classification number: G11C7/062 ,  G11C7/067 ,  G11C16/28

Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

Abstract translation: 提供了一种用于控制在操作模式和待机模式之间切换的读出放大器中的参考节点的电路。 参考节点在工作模式下提供参考电压。 电路可以包括用于在进入待机模式时使参考节点进入起始电压的电路，用于将参考节点保持在备用模式下的预充电电压的电路，以及用于提供比较电压更接近的电路 到预充电电压比启动电压。 还可以包括牵引电路以将参考节点拉向电源电压。 此外，控制器可以在进入待机模式时激活拉电路，并且当参考节点处的电压达到比较电压时禁止拉电路。

公开(公告)号：US20030141559A1

公开(公告)日：2003-07-31

申请号：US10325653

申请日：2002-12-20

Applicant: STMicroelectronics S.r.I.

Inventor： Alessandro Moscatelli ,  Giuseppe Croce

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119 ,  H01L021/3205 ,  H01L021/8234 ,  H01L021/4763

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42368 ,  H01L29/512 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second portion having a second thickness differing from the first thickness.

Abstract translation: 集成在半导体材料晶片中的金属氧化物半导体晶体管包括位于晶片表面上并包括栅极氧化物层的栅极结构。 栅极氧化物层包括具有第一厚度的第一部分和具有不同于第一厚度的第二厚度的第二部分。

公开(公告)号：US20030134481A1

公开(公告)日：2003-07-17

申请号：US10350403

申请日：2003-01-23

Applicant: STMicroelectronics S.r.I.

Inventor： Piero Fallica

IPC: H01L021/331 ,  H01L031/0392

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/12 ,  H01L2924/00011 ,  H01L2224/80001

Abstract: Integrated circuit including a power component with vertical current flow and at least one low or medium voltage component, the at least one low or medium voltage component formed in a first semiconductor layer separated from a second semiconductor layer by an insulating material layer. The power component with vertical current flow is formed in the second semiconductor layer, and excavations are formed in the insulating material layer which extend from a free surface of the first semiconductor layer to the second semiconductor layer, said excavations having lateral walls of insulating material and being filled up with a conductor material in order to electrically contact active regions of the power component in the second semiconductor layer by electrodes placed on the free surface of the first semiconductor layer.

Abstract translation: 集成电路包括具有垂直电流的功率分量和至少一个低或中等电压分量，所述至少一个低或中等电压分量形成在通过绝缘材料层与第二半导体层分离的第一半导体层中。 具有垂直电流的功率部件形成在第二半导体层中，并且在从第一半导体层的自由表面延伸到第二半导体层的绝缘材料层中形成挖掘，所述挖掘具有绝缘材料的侧壁， 被填充有导体材料，以便通过放置在第一半导体层的自由表面上的电极与第二半导体层中的功率部件的有源区域电接触。

公开(公告)号：US20030133313A1

公开(公告)日：2003-07-17

申请号：US10331155

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Marcello Criscione

IPC: H02M003/335

CPC classification number: H02M3/1588 ,  Y02B70/1466

Abstract: A synchronous rectifier circuit operates as a high-efficiency DC/DC converter for mixed step-up/step-down applications, and includes an input terminal receiving a voltage signal, a second input terminal node connected to an external inductor, and an output terminal. A power switch may be connected between the second input terminal node and the output terminal to generate on its output a voltage at one terminal of the inductor. A driver circuit is provided for driving the power switch, and a comparator senses the potential difference between the output and input terminals and produces an enable signal for the driver circuit. The comparator may be a wide pass-band comparator forcing prompt triggering of the regulation loop in the rectifier.

Abstract translation: 同步整流电路用作用于混合升压/降压应用的高效率DC / DC转换器，并且包括接收电压信号的输入端子，连接到外部电感器的第二输入端子节点和输出端子 。 电源开关可以连接在第二输入端子节点和输出端子之间，以在其输出端产生电感器一端的电压。 提供驱动电路用于驱动电源开关，比较器检测输出端和输入端之间的电位差，产生驱动电路的使能信号。 比较器可以是宽的通带比较器，迫使整流器中调节回路的触发迅速。

公开(公告)号：US20030128449A1

公开(公告)日：2003-07-10

申请号：US10033726

申请日：2001-12-28

Applicant: STMicroelectronics S.r.I.

Inventor： Angelo Dati ,  Davide Giovenzana

IPC: G11B020/10 ,  G11B005/09 ,  G11B005/596

CPC classification number: G11B20/10287 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10296

Abstract: A system provides two distinct solutions for encoding and decoding servo positioning data for a hard disk drive. A first solution includes: encoding each group of four bits of a pattern signal in a Matched Spectral Null (MSN) format through an intermediate rate {fraction (4/6)} code; providing a duplicated bit for each bit of the six bit code word obtained with the previous step. A second solution includes: encoding each group of four bit of the pattern signal adding a parity check bit as an intermediate rate null code; encoding each of the five bits using the biphase map. Both solutions include subsequently: reading a servo wedge information signal using a read and write channel of the hard disk drive; and using a trellis Partial Response decoding scheme matched to said encoded word for obtaining angular and radial information for the head positioning.

Abstract translation: 系统为硬盘驱动器的伺服定位数据的编码和解码提供了两个不同的解决方案。 第一个解决方案包括：通过中间速率4/6代码以匹配光谱空（MSN）格式对每组4位模式信号进行编码; 为前一步获得的六位码字的每一位提供一个复制位。 第二个解决方案包括：对每组4位模式信号进行编码，将奇偶校验位作为中间速率⅘码; 使用双相图编码五位中的每一位。 这两种解决方案包括：使用硬盘驱动器的读和写通道读取伺服楔信息信号; 以及使用与所述编码字匹配的网格部分响应解码方案来获得头部定位的角度和径向信息。

公开(公告)号：US20030122221A1

公开(公告)日：2003-07-03

申请号：US10323961

申请日：2002-12-18

Applicant: STMicroelectronics S.r.I.

Inventor： Giorgio De Santi ,  Luca Zanotti

IPC: H01L023/58

CPC classification number: H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.

Abstract translation: 用于在集成电路上形成最终钝化层的工艺包括通过高密度等离子体化学气相沉积在集成电路的表面上形成保护膜的步骤。