公开(公告)号：US11289572B1

公开(公告)日：2022-03-29

申请号：US17100963

申请日：2020-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Pu Chiu ,  Tzung-Ying Lee ,  Dien-Yang Lu ,  Chun-Kai Chao ,  Chun-Mao Chiou

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L21/02 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first contact plug between the first epitaxial layer and the second epitaxial layer, a third epitaxial layer and a fourth epitaxial layer adjacent to another side of the first gate structure, and a second contact plug between the third epitaxial layer and the fourth epitaxial layer. Preferably, a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug and a bottom surface of the third epitaxial layer is lower than a bottom surface of the second contact plug.

公开(公告)号：US11289489B2

公开(公告)日：2022-03-29

申请号：US16812384

申请日：2020-03-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chieh-Te Chen

IPC: H01L27/108 ,  H01L21/311 ,  H01L21/02 ,  H01L49/02

Abstract: A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.

公开(公告)号：US11289368B2

公开(公告)日：2022-03-29

申请号：US16884081

申请日：2020-05-27

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L27/12

Abstract: A semiconductor device is provided. The semiconductor device includes a device substrate, having a device structure layer and a buried dielectric layer, wherein the buried dielectric layer is disposed on a semiconductor layer of the device structure layer. A metal layer is disposed on the buried dielectric layer and surrounded by a first inter-layer dielectric (ILD) layer. A region of the metal layer has a plurality of openings. The buried dielectric layer has an air gap under and exposing the region of the metal layer with the openings. A second ILD layer is disposed on the metal layer and sealing the air gap at the openings of the metal layer.

公开(公告)号：US20220093778A1

公开(公告)日：2022-03-24

申请号：US17100935

申请日：2020-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Hsing Chen ,  Yu-Ming Hsu ,  Tsung-Mu Yang ,  Yu-Ren Wang

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/67 ,  H01L21/768

Abstract: A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

公开(公告)号：US20220093584A1

公开(公告)日：2022-03-24

申请号：US17075707

申请日：2020-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Te-Wei Yeh ,  Yi-Chun Chen

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L21/306 ,  H01L21/765 ,  H01L21/8252

Abstract: A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

公开(公告)号：US20220085284A1

公开(公告)日：2022-03-17

申请号：US17023382

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Jung Liu ,  Chau-Chung Hou ,  Ang Chan ,  Kun-Ju Li ,  Wen-Chin Lin

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

公开(公告)号：US20220085210A1

公开(公告)日：2022-03-17

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US20220085184A1

公开(公告)日：2022-03-17

申请号：US17068840

申请日：2020-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Heng-Ching Lin ,  Yu-Teng Tseng ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

公开(公告)号：US20220084928A1

公开(公告)日：2022-03-17

申请号：US17073392

申请日：2020-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L27/01

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other.

公开(公告)号：US20220059697A1

公开(公告)日：2022-02-24

申请号：US17065396

申请日：2020-10-07

Applicant: United Microelectronics Corp.

Inventor： Ching-Chung Yang

IPC: H01L29/78 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device includes: forming a first transistor including: forming a plurality of lightly doped regions in a substrate; forming a first gate structure on the substrate, the first gate structure covering portions of the plurality of lightly doped regions and a portion of the substrate; forming first spacers on sidewalls of the first gate structure; forming doped region in the lightly doped regions; forming an etching stop layer on the substrate; patterning the etching stop layer and the first gate structure to form a second gate structure, and to form a plurality of trenches between the second gate structure and the first spacers; and forming a first dielectric layer on the substrate to cover the etching stop layer and fill the plurality of trenches. The first dielectric layer filled in the trenches is used as virtual spacers.