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    Sequence estimation system and method
    432.
    发明授权
    Sequence estimation system and method 有权

    公开(公告)号：US11582073B1

    公开(公告)日：2023-02-14

    申请号：US17588360

    申请日：2022-01-31

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Amir Dabbagh

    IPC: H04L25/03

    Abstract: A system comprising a processing circuitry configured to: obtain a first ordered sequence of symbols associated with a corresponding second ordered sequence of transmitted symbols and including one or more errors, the errors being discrepancies between given symbols of the first ordered sequence and corresponding symbols of the second ordered sequence; determine, for each symbol of the first ordered sequence of symbols, an estimated transmitted symbol, utilizing a Decision Feedback Equalizer (DFE); and determine if the estimated transmitted symbol of a given symbol of the first ordered sequence of symbols, satisfies a saturation threshold condition; and determine an error hypothesis identifying one or more of the errors by comparing the estimated transmitted symbol of at least one symbol of the first ordered sequence of symbols with one or more pairs of thresholds.

    Processor with conditional-fence commands excluding designated memory regions
    433.
    发明授权
    Processor with conditional-fence commands excluding designated memory regions 有权

    公开(公告)号：US11580036B1

    公开(公告)日：2023-02-14

    申请号：US17385962

    申请日：2021-07-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo ,  Shahaf Shuler ,  George Elias ,  Nizan Atias ,  Adi Maymon

    IPC: G06F12/14 ,  G06F9/30 ,  G06F12/02

    Abstract: An apparatus includes a processor, configured to designate a memory region in a memory, and to issue (i) memory-access commands for accessing the memory and (ii) a conditional-fence command associated with the designated memory region. Memory-Access Control Circuitry (MACC) is configured, in response to identifying the conditional-fence command, to allow execution of the memory-access commands that access addresses within the designated memory region, and to defer the execution of the memory-access commands that access addresses outside the designated memory region, until completion of all the memory-access commands that were issued before the conditional-fence command.

    Low-latency delivery of in-band telemetry data
    435.
    发明授权
    Low-latency delivery of in-band telemetry data 有权

    公开(公告)号：US11558310B2

    公开(公告)日：2023-01-17

    申请号：US17348801

    申请日：2021-06-16

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Matty Kadosh ,  Yuval Shpigelman ,  Omer Shabtai ,  Yonatan Piasetsky ,  Aviv Kfir ,  Alan Lo ,  Marian Pritsak

    IPC: H04L47/6275 ,  H04L43/106 ,  H04L43/0888 ,  H04L47/62 ,  H04L43/10 ,  H04L47/263

    Abstract: A network device includes processing circuitry and a plurality of ports. The ports connect to a communication network. The processing circuitry is configured to receive, via an input port, data packets and probe packets that are addressed to a common output port, to store the data packets in a first queue and the probe packets in a second queue, both the first queue and the second queue are served by the output port, to produce telemetry data indicative of a state of the network device, based on a processing path that the data packets traverse within the network device, to schedule transmission of the data packets from the first queue at a first priority, and schedule transmission of the probe packets from the second queue at a second priority higher than the first priority, and to modify the scheduled probe packets so as to carry the telemetry data.

    Expandable queue
    436.
    发明授权
    Expandable queue 有权

    公开(公告)号：US11558309B1

    公开(公告)日：2023-01-17

    申请号：US17369992

    申请日：2021-07-08

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ilan Pardo

    IPC: H04L47/625 ,  H04L49/90 ,  H04L49/9005 ,  H04L47/62

    Abstract: A network device includes packet processing circuitry and queue management circuitry. The packet processing circuitry is configured to transmit and receive packets to and from a network. The queue management circuitry is configured to store, in a memory, a queue for queuing data relating to processing of the packets, the queue including a primary buffer and an overflow buffer, to choose between a normal mode and an overflow mode based on a defined condition, to queue the data only in the primary buffer when operating in the normal mode, and, when operating in the overflow mode, to queue the data in a concatenation of the primary buffer and the overflow buffer.

    Network flow sampling fairness
    437.
    发明授权
    Network flow sampling fairness 有权

    公开(公告)号：US11558304B2

    公开(公告)日：2023-01-17

    申请号：US17687642

    申请日：2022-03-06

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alan Lo ,  Matty Kadosh ,  Marian Pritsak ,  Yonatan Piasetsky

    IPC: H04L47/2483 ,  H04L47/2441 ,  H04L43/0811 ,  H04L43/16 ,  H04L47/20

    Abstract: In one embodiment, a network flow sampling system includes packet processing circuitry to process data packets of multiple network flows, and an adaptive policer to, for each one network flow of the multiple network flows compute a quantity of flow-specific sampling credits to be assigned to the one network flow responsively to a quantity of the network flows currently being processed by the packet processing circuitry, assign the flow-specific sampling credits to the one network flow, sample at least one of the data packets of the one network flow responsively to availability of the flow-specific sampling credits of the one network flow yielding sampled data, while applying sampling fairness among the network flows, and remove at least one of the flow-specific sampling credits of the one network flow from availability responsively to sampling the at least one data packet of the one network flow.

    Accurate Time-Stamping of Outbound Packets
    438.
    发明申请
    Accurate Time-Stamping of Outbound Packets 有权

    公开(公告)号：US20220416925A1

    公开(公告)日：2022-12-29

    申请号：US17359667

    申请日：2021-06-28

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Wojciech Wasko ,  Natan Manevich ,  Hillel Chapman ,  Roi Geuli ,  Eyal Serbro

    IPC: H04J3/06

    Abstract: A network device includes a port, a transmission pipeline and a time-stamping circuit. The port is configured for connecting to a network. The transmission pipeline includes multiple pipeline stages and is configured to process packets and to send the packets to the network via the port. The time-stamping circuit is configured to temporarily suspend at least some processing of at least a given packet in the transmission pipeline, to verify whether a pipeline stage having a variable processing delay, located downstream from the time-stamping circuit, meets an emptiness condition, and, only when the pipeline stage meets the emptiness condition, to time-stamp the given packet and resume the processing of the given packet.

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