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公开(公告)号:US20210118725A1
公开(公告)日:2021-04-22
申请号:US17068112
申请日:2020-10-12
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Franck JULIEN , Abderrezak MARZAKI
IPC: H01L21/762 , H01L21/308 , H01L21/311 , H01L21/306 , H01L21/02 , H01L25/18 , H01L25/16
Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.
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公开(公告)号:US20210117532A1
公开(公告)日:2021-04-22
申请号:US17071094
申请日:2020-10-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Olivier Giaume
IPC: G06F21/44
Abstract: An embodiment device comprises a first processing unit configured to process an initial data line and deliver a first processed data line, a first delay unit coupled to the output of the first processing unit and configured to deliver a delayed first processed data line delayed by a first delay, a second delay unit configured to deliver the delayed initial data line delayed by a second delay, a second processing unit coupled to the output of the second delay unit and configured to process the delayed initial data line and deliver a delayed second processed data line, and a comparison unit configured to compare the contents of the delayed first and second processed data lines and deliver a non-authentication signal if the contents are not identical, the first and second delays being equal to a variable value.
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公开(公告)号:US20210109711A1
公开(公告)日:2021-04-15
申请号:US17038774
申请日:2020-09-30
Inventor: Rene Peyrard , Fabrice Romain , Jean-Michel Derien , Christophe Eichwald
Abstract: An embodiment relates to a method for processing masked data using a processor comprising an arithmetic and logic unit, in which the masked data remain masked during their processing in the arithmetic and logic unit.
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公开(公告)号:US10971578B2
公开(公告)日:2021-04-06
申请号:US16596673
申请日:2019-10-08
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor: Abderrezak Marzaki , Pascal Fornara
IPC: H01L49/02 , H01L21/02 , H01L21/283 , H01L21/306 , H01L27/11521 , H01L27/11531 , H01L27/06 , H01L27/10
Abstract: The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.
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公开(公告)号:US10955898B2
公开(公告)日:2021-03-23
申请号:US15989731
申请日:2018-05-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Jonathan Cottinet , Jean Claude Bini
Abstract: An electronic device includes an appended module coupled to a core having a standby state comprising a first power supply circuit, a first clock and a circuit that recognizes multiple vocal commands timed by the first clock. The appended module includes a second power supply circuit independent of the first power supply circuit, a second clock independent of the first clock and having a frequency lower than that of the first clock, digital unit timed by the second clock including a sound capture circuit that delivers a processed sound signal, and a processing unit configured in order, in the presence of a parameter of the processed sound signal greater than a threshold, to analyze the content of the processed sound signal and to deliver, when the content of the sound signal comprises a reference pattern, an activating signal to the core that can take it out of its standby state.
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公开(公告)号:US10950559B2
公开(公告)日:2021-03-16
申请号:US16436747
申请日:2019-06-10
Inventor: Mathieu Lisart , Bruce Rae
Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
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公开(公告)号:US10943862B2
公开(公告)日:2021-03-09
申请号:US16242529
申请日:2019-01-08
Inventor: Abderrezak Marzaki , Arnaud Regnier , Stephan Niel
IPC: H01L23/522 , H01L21/762 , H01L21/02 , H01L21/8238 , H01L29/94 , H01L29/66 , H01L27/08
Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.
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448.
公开(公告)号:US20210035996A1
公开(公告)日:2021-02-04
申请号:US16939603
申请日:2020-07-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Franck JULIEN , Abderrezak MARZAKI
IPC: H01L27/11531 , H01L27/11521 , H01L29/788 , H01L21/02 , H01L21/311 , H01L21/265 , H01L21/28 , H01L29/66
Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.
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公开(公告)号:US20210028700A1
公开(公告)日:2021-01-28
申请号:US16933277
申请日:2020-07-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Michel CUENCA , Sebastien ORTET
IPC: H02M3/158
Abstract: A switched-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes, selectively connected in parallel, at least three capacitors. The selective connection of the capacitors is made according to a value of an internal power supply voltage of the switched-mode power supply.
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450.
公开(公告)号:US20210018458A1
公开(公告)日:2021-01-21
申请号:US16928551
申请日:2020-07-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor: Matthias VIDAL-DHO , Quentin HUBERT , Pascal FORNARA
Abstract: Moisture that is possibly present in an integrated circuit is detected autonomously by the integrated circuit itself. An interconnect region of the integrated circuit includes a metal level with a first track and a second track which are separated by a dielectric material. A detection circuit applies a potential difference between the first and second tracks. A current circulating in one of the first and second tracks in response to the potential difference is measured and compared to a threshold. If the current exceeds the threshold, this is indicative of the presence of moisture which renders said dielectric material less insulating.
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