公开(公告)号：US11996465B2

公开(公告)日：2024-05-28

申请号：US17486000

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

CPC classification number: H01L29/66234 ,  H01L21/22 ,  H01L29/0649 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11978710B2

公开(公告)日：2024-05-07

申请号：US17359872

申请日：2021-06-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/66 ,  H01L29/06

CPC classification number: H01L23/66 ,  H01L21/76286 ,  H01L29/0646 ,  H01L29/0649 ,  H01L2223/6688

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

公开(公告)号：US11949035B2

公开(公告)日：2024-04-02

申请号：US17546503

申请日：2021-12-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Denis Rideau ,  Dominique Golanski ,  Alexandre Lopez ,  Gabriel Mugny

IPC: H01L31/107 ,  H01L31/18

CPC classification number: H01L31/107 ,  H01L31/186

Abstract: A single photon avalanche diode (SPAD) includes a PN junction in a semiconductor well doped with a first type of dopant. The PN junction is formed between a first region doped with the first type of dopant and a second region doped with a second type of dopant opposite to the first type of dopant. The first doped region is shaped so as to incorporate local variations in concentration of dopants that are configured, in response to a voltage between the second doped region and the semiconductor well that is greater than or equal to a level of a breakdown voltage of the PN junction, to generate a monotonic variation in the electrostatic potential between the first doped region and the semiconductor well.

公开(公告)号：US20240063280A1

公开(公告)日：2024-02-22

申请号：US18230423

申请日：2023-08-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Franck JULIEN ,  Julien DELALLEAU ,  Julien DURA ,  Julien AMOUROUX ,  Stephane MONFRAY

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/7833 ,  H01L29/42368 ,  H01L29/401

Abstract: A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.

公开(公告)号：US11908809B2

公开(公告)日：2024-02-20

申请号：US17325999

申请日：2021-05-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Eric Sabouret ,  Krysten Rochereau ,  Olivier Hinsinger ,  Flore Persin-Crelerot

IPC: H01L23/00 ,  H05K3/34 ,  H01L23/498 ,  H01L21/66

CPC classification number: H01L23/562 ,  H01L22/34 ,  H01L23/49816 ,  H01L24/05 ,  H05K3/3436 ,  H01L2224/05093 ,  H01L2924/14

Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.

公开(公告)号：US20240053202A1

公开(公告)日：2024-02-15

申请号：US18186102

申请日：2023-03-17

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jerome VAILLANT ,  Francois DENEUVILLE ,  Axel CROCHERIE ,  Alain OSTROVSKY

IPC: G01J3/447 ,  G01J3/18

CPC classification number: G01J3/447 ,  G01J3/18

Abstract: The present description concerns a polarimetric image sensor formed inside and on top of a semiconductor substrate, the second comprising a plurality of pixels, each comprising: —a photosensitive region formed in the semiconductor substrate; —a diffraction structure formed on the side of an illumination surface of the photosensitive region; and —a polarization structure formed on the side of the diffraction structure opposite to the photosensitive region.

公开(公告)号：US11895417B2

公开(公告)日：2024-02-06

申请号：US17667485

申请日：2022-02-08

Applicant: STMicroelectronics France ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Celine Mas ,  Matteo Maria Vignetti ,  Francois Agut

IPC: H04N25/709 ,  H04N25/75 ,  H01L27/146

CPC classification number: H04N25/709 ,  H04N25/75 ,  H01L27/1463 ,  H01L27/14609

Abstract: The present description describes an image sensor including an array of pixels arranged inside and on top of a region of a semiconductor substrate electrically insulated from the rest of the substrate by insulating trenches crossing the substrate, each pixel including a photoconversion area and at least two assemblies, each including a memory area and a transfer gate coupling the memory area to the photoconversion area, and a circuit configured to apply, for each pixel and at least during each integration phase, a bias voltage different from ground to a portion of the substrate having the pixel arranged inside and on top of it.

公开(公告)号：US20240040781A1

公开(公告)日：2024-02-01

申请号：US18484906

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00

CPC classification number: H10B20/367 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

公开(公告)号：US20240023468A1

公开(公告)日：2024-01-18

申请号：US18190901

申请日：2023-03-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS SA

Inventor： Alain FLEURY ,  Stephane MONFRAY ,  Philippe CATHELIN ,  Bruno REIG ,  Vincent PUYAL

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8613 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8828

Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.

公开(公告)号：US20240023467A1

公开(公告)日：2024-01-18

申请号：US18186103

申请日：2023-03-17

Applicant: STMicroelectronics (Crolles 2) SAS ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Stephane MONFRAY ,  Alain FLEURY ,  Bruno REIG

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/861 ,  H10N70/231 ,  H10N70/823 ,  H10N70/063 ,  H10N70/8828

Abstract: The present description concerns a switch based on a phase-change material comprising: a region of the phase-change material; a heating element electrically insulated from the region of the phase-change material; and one or a plurality of pillars extending in the region of the phase-change material, the pillar(s) being made of a material having a thermal conductivity greater than that of the phase-change material.