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    Hysteresis compensation in a disc drive
    471.
    发明授权
    Hysteresis compensation in a disc drive 有权

    公开(公告)号：US10068598B2

    公开(公告)日：2018-09-04

    申请号：US15915520

    申请日：2018-03-08

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Reed D. Hanson ,  Kenneth A. Haapala ,  Dwight R. Kinney ,  Xinghui Huang

    IPC: G11B5/55 ,  G11B5/48 ,  G11B5/596

    CPC classification number: G11B5/556 ,  G11B5/4873 ,  G11B5/59622

    Abstract: Systems and methods for compensating for hysteresis in a disc drive are described. In one embodiment, a method may use an inverse hysteresis model to linearize effects of hysteresis of a microactuator in the disc drive. The hysteresis model may be a Coleman-Hodgdon hysteresis model. The hysteresis of the microactuator may be characterized, and the inverse hysteresis model may be based at least in part on the characterization. The inverse hysteresis model may be used to implement a digital filter. The digital filter may be employed in series with the microactuator to linearize the effects of hysteresis.

    Configuration element for printed circuit board assemblies
    476.
    发明授权
    Configuration element for printed circuit board assemblies 有权

    公开(公告)号：US10051729B2

    公开(公告)日：2018-08-14

    申请号：US15271525

    申请日：2016-09-21

    Applicant: Seagate Technology LLC

    Inventor： David Michael Davis ,  Gary Edward Webb

    IPC: H05K7/00 ,  H05K1/02 ,  H05K3/34 ,  H05K1/18

    Abstract: A printed circuit board assembly includes a printed circuit board having a plurality of signal lanes. The PCBA also includes at least one application-specific integrated circuit operatively mounted to the printed circuit board and connected with the plurality of signal lanes. The PCBA includes a first configuration element operatively mounted to the printed circuit board in a first orientation and at a first location and having a first bridging element for providing an electrical connection between at least a first pair of signal lanes selected from the plurality of signal lanes. The first configuration element also includes a second bridging element so that if the first configuration element were operatively mounted to the printed circuit board in a different, second orientation relative to the printed circuit board, the second bridging element would provide an electrical connection between at least a second pair of signal lanes.

    Selectable readers for better performance
    477.
    发明授权
    Selectable readers for better performance 有权

    公开(公告)号：US10049690B1

    公开(公告)日：2018-08-14

    申请号：US15671482

    申请日：2017-08-08

    Applicant: Seagate Technology LLC

    Inventor： Victor Sapozhnikov ,  Taras Grigorievich Pokhil ,  Mohammed Shariat Ullah Patwari

    IPC: G11B5/127 ,  G11B5/31

    Abstract: A method of forming a read head. The method includes forming first and second read sensors that are substantially trapezoidal in shape. A first read measurement is performed on a storage medium using the first read sensor. A second read measurement is performed on the storage medium using the second read sensor. Based on a comparison of the first and second read measurements to a predetermined quantity, either the first read sensor or the second read sensor is selected to be operational in a data storage device.

    Method to shorten hash chains in lempel-ziv compression of data with repetitive symbols
    478.
    发明授权
    Method to shorten hash chains in lempel-ziv compression of data with repetitive symbols 有权

    公开(公告)号：US10048867B2

    公开(公告)日：2018-08-14

    申请号：US14976236

    申请日：2015-12-21

    Applicant: Seagate Technology LLC

    Inventor： Ning Chen

    IPC: G06F7/00 ,  G06F17/30 ,  G06F3/06 ,  H03M7/30

    Abstract: An apparatus having a circuit is disclosed. The circuit may be configured to (i) generate a sequence of hash values in a table from a stream of data values with repetitive values, (ii) find two consecutive ones of the hash values in the sequence that have a common value and (iii) create a shortened hash chain by generating a pointer in the table at an intermediate location that corresponds to a second of the two consecutive hash values. The pointer generally points forward in the table to an end location that corresponds to a last of the data values in a run of the data values.

    Open block refresh management
    479.
    发明授权
    Open block refresh management 有权

    公开(公告)号：US10048863B1

    公开(公告)日：2018-08-14

    申请号：US15170874

    申请日：2016-06-01

    Applicant: Seagate Technology LLC

    Inventor： Ryan James Goss ,  Antoine Khoueir ,  Ara Patapoutian

    IPC: G11C7/00 ,  G06F3/06

    Abstract: Systems and methods are disclosed for open block refresh management. In certain embodiments, an apparatus may comprise a circuit configured to monitor an amount of time a block of a solid-state memory remains in an open state where the block has not been fully filled with data, and in response to reaching an open block time limit, compare an amount of the block already written with data against a threshold amount. When less than a threshold amount of the block has been written with data, the circuit may refresh data from a last N pages from the block by writing the data to a new location, N being a number of pages less than all pages in the block. When more than the threshold amount of the block has been written with data, the circuit may fill a remaining unwritten amount of the block with dummy data.

    BACKGROUND READS TO CONDITION PROGRAMMED SEMICONDUCTOR MEMORY CELLS
    480.
    发明申请
    BACKGROUND READS TO CONDITION PROGRAMMED SEMICONDUCTOR MEMORY CELLS 审中-公开

    公开(公告)号：US20180225164A1

    公开(公告)日：2018-08-09

    申请号：US15498595

    申请日：2017-04-27

    Applicant: Seagate Technology, LLC

    Inventor： Antoine Khoueir ,  Stacey Secatch ,  Kevin Gomez ,  Ryan Goss

    IPC: G06F11/07 ,  G11C16/16 ,  G11C16/34 ,  G11C16/26

    CPC classification number: G06F11/076 ,  G06F11/073 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459

    Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

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