公开(公告)号：US20140176216A1

公开(公告)日：2014-06-26

申请号：US14134167

申请日：2013-12-19

Applicant: Commissariat à I'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Yvain Thonnart ,  Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel

IPC: H03K3/012 ,  H01L27/12 ,  G05F3/02

CPC classification number: H03K3/012 ,  G05F3/02 ,  G06F1/10 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648

Abstract: The invention relates to an integrated circuit comprising: a block comprising: first (38) and second (40) oppositely doped semiconductor wells; standard cells (42, 43) placed next to one another, each standard cell (42) comprising first transistors (60, 62), and a clock tree cell (30) encircled by standard cells, the clock tree cell (30) comprising: a third semiconductor well (104) having the same doping type as the doping of the first well (38); second transistors (100, 102); a semiconductor strip (106) extending continuously around the third well (104), and having the opposite doping type to the doping of the third well, so as to electrically isolate the third well (104) from the first well (38).

Abstract translation: 本发明涉及一种集成电路，包括：块，包括：第一（38）和第二（40）相对掺杂的半导体阱; 时钟树单元（30）包括：标准单元（42,43），其彼此相邻放置，每个标准单元（42）包括第一晶体管（60,62）和由标准单元包围的时钟树单元（30） 具有与所述第一阱（38）的掺杂相同的掺杂类型的第三半导体阱（104）; 第二晶体管（100,102）; 围绕第三阱（104）连续延伸的半导体条（106），并且具有与第三阱的掺杂相反的掺杂类型，从而将第三阱（104）与第一阱（38）电隔离。

公开(公告)号：US20140156248A1

公开(公告)日：2014-06-05

申请号：US14084727

申请日：2013-11-20

Applicant: STMICROELECTRONICS SA

Inventor： JEAN-ROBERT MANOUVRIER

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G09B23/18

Abstract: A simulation method for a P-I-N junction photodiode uses a model that may include a diode model configured to characterize electrical behavior of the P-I-N junction photodiode, and an input for applying a fictitious electrical signal representing optical power received by the P-I-N junction photodiode. A current source model may be coupled to the diode model and may have a transient response to a variation of the fictitious electrical signal, based upon a sum of a first first-order transient response with a time constant based upon to a transit time of carriers in a depletion region of the P-I-N junction, and a second first-order transient response with a time constant based upon a diffusion time of carriers outside of the depletion region. The first and second responses may be respectively weighted by a length of the depletion region and a length of the P-I-N junction outside the depletion region.

Abstract translation: 用于P-I-N结光电二极管的模拟方法使用可以包括被配置为表征P-I-N结光电二极管的电气行为的二极管模型的模型，以及用于施加表示由P-I-N结光电二极管接收的光功率的虚拟电信号的输入。 电流源模型可以耦合到二极管模型，并且可以基于第一一阶瞬态响应与基于载波的传输时间的时间常数的和来对虚拟电信号的变化进行瞬态响应 在PIN结的耗尽区和基于耗尽区外的载流子的扩散时间的时间常数的第二一阶瞬态响应。 第一和第二响应可以分别由耗尽区的长度和耗尽区之外的P-I-N结的长度加权。

公开(公告)号：US20140075726A1

公开(公告)日：2014-03-20

申请号：US14084394

申请日：2013-11-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： David Petit ,  Sylvain Joblot ,  Pierre Bar ,  Jean-Francois Carpentier ,  Pierre Dautriche

IPC: H03H3/02

CPC classification number: H03H3/02 ,  G01N29/022 ,  G02F1/133707 ,  H03H3/04 ,  H03H9/0028 ,  H03H9/02102 ,  H03H9/175 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49155

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract translation: 一种制造晶片的方法，其上形成有谐振器，每个谐振器包括在半导体衬底上方的一叠层，其从衬底表面依次包括：布拉格反射镜; 由具有与所有其它堆叠层相反的符号的声速的温度系数的材料制成的补偿层; 和压电谐振器，该方法包括以下连续步骤：a）沉积补偿层; 和b）由于沉积方法而减小补偿层的厚度不等式，使得该层在每个谐振器的电平上具有相同的厚度，优于2％以内，优选在1％以内。

公开(公告)号：US20140015002A1

公开(公告)日：2014-01-16

申请号：US13921436

申请日：2013-06-19

Applicant: STMicroelectronics SA

Inventor： Pascal FONTENEAU

IPC: H01L29/749

CPC classification number: H01L29/749 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/1203 ,  H01L27/1207

Abstract: A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated there-from by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.

Abstract translation: 保护在被布置在绝缘层本身上的SOI型半导体层中形成的过电压的MOS晶体管，其本身布置在半导体衬底上，该半导体衬底包括至少部分地在MOS晶体管下方形成在衬底中的横向场效应控制晶闸管，场效应转 在所述晶体管的至少一部分在所述MOS晶体管的主电极的至少一部分延伸的区域之外，所述晶闸管的所述绝缘层，所述晶闸管的阳极和阴极分别连接到所述漏极和源极 MOS晶体管，从而在MOS晶体管的漏极和源极之间的正过电压的情况下晶闸管导通。

公开(公告)号：US20130321057A1

公开(公告)日：2013-12-05

申请号：US13904606

申请日：2013-05-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Dimitri Soussan ,  Sylvain Majcherczak ,  Alexandre Valentian ,  Marc Belleville

IPC: H03K19/0185

CPC classification number: H03K19/018578 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract translation: 集成电路可以包括包括包括MOSFET晶体管的子组件的缓冲级的数字输出端口。 一个子组件可以包括具有连接到公共高电压的源的两个上拉晶体管，并且具有连接到连接到输出端子的公共节点的漏极。 另一个子组件可以包括具有连接到公共低电压的源的下拉晶体管，并且具有连接到公共节点的漏极。 上拉和下拉晶体管形成在FDSOI衬底的薄半导体层中。 衬底可以包括厚半导体层和分离薄和厚半导体层的氧化物层。 面向上拉和下拉晶体管的厚半导体层的区域可以连接到被配置为改变上拉和下拉晶体管的阈值电压的电路。

公开(公告)号：US08598938B2

公开(公告)日：2013-12-03

申请号：US13666727

申请日：2012-11-01

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Johan Bourgeat

IPC: H03K17/687

CPC classification number: H03K17/063 ,  H01L27/0262

Abstract: A power switch includes first and second MOS transistors in series between first and second nodes. Both the first and second transistors have a gate coupled to its substrate. First and second resistive elements are coupled between the gate of the first transistor and the first node, and between the gate of the second transistor and the second node, respectively. A triac is coupled between the first and second nodes. The gate of the triac is coupled to a third node common to the first and second transistors. A third MOS transistor has a first conduction electrode coupled to the gate of the first transistor and a second conduction electrode coupled to the gate of the second transistor.

Abstract translation: 电源开关包括在第一和第二节点之间串联的第一和第二MOS晶体管。 第一和第二晶体管都具有耦合到其衬底的栅极。 第一和第二电阻元件分别耦合在第一晶体管的栅极和第一节点之间，以及第二晶体管的栅极和第二节点之间。 三端双向可控硅开关元件耦合在第一和第二节点之间。 三端双向可控硅开关元件的栅极耦合到第一和第二晶体管共同的第三节点。 第三MOS晶体管具有耦合到第一晶体管的栅极的第一导电电极和耦合到第二晶体管的栅极的第二导电电极。

公开(公告)号：US20130283119A1

公开(公告)日：2013-10-24

申请号：US13919865

申请日：2013-06-17

Applicant: STMicroelectronics SA

Inventor： Vincent Heinrich ,  Julien Begey

IPC: H03M13/13

CPC classification number: H03M13/13 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1171 ,  H03M13/6502 ,  H03M13/6505

Abstract: Method of elementary updating a check node of a non-binary LDPC code during a decoding of a block encoded with said LDPC code, comprising receiving a first input message (U) and a second input message (V) each comprising nm doublets having a symbol and an associated metric, delivering an output message (S) possessing nm output doublets by computing a matrix of nm2 combined doublets on the basis of a combination of the doublets of the two input messages (U,V), and reducing the number of the combined doublets so as to obtain the nm output doublets of the output message (S) possessing the nm largest or lowest metrics. The method further includes tagging redundant symbols within each input message (U, V) and fixing same at a reference value, the value of the metric of each combined doublet resulting from a combination of at least one doublet comprising a tagged redundant symbol.

Abstract translation: 在用所述LDPC码编码的块的解码期间，对非二进制LDPC码的校验节点进行基本更新的方法，包括接收第一输入消息（U）和第二输入消息（V），每个包括具有符号 和相关联的度量，通过基于两个输入消息（U，V）的双重组合的计算nm2组合双精度的矩阵来传送具有nm输出双精度的输出消息（S），并且减少 组合双重，以获得具有nm最大或最小度量的输出消息（S）的nm输出双倍。 该方法还包括在每个输入消息（U，V）中标记冗余符号并且以参考值固定相同的值，由包括标记的冗余符号的至少一个双工的组合产生的每个组合双精度的度量值。

公开(公告)号：US20130264677A1

公开(公告)日：2013-10-10

申请号：US13859418

申请日：2013-04-09

Applicant: STMICROELECTRONICS SA

Inventor： Philippe GALY ,  Jean JIMENEZ

IPC: H01L27/02 ,  H01L21/77

CPC classification number: H01L27/0207 ,  H01L21/76264 ,  H01L21/77 ,  H01L27/088 ,  H01L27/1211 ,  H01L29/0692 ,  H01L29/435 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7825

Abstract: At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.

Abstract translation: 至少三个导电块设置在隔离区内; 并且它们中的至少两个被隔离区域的一部分相互分离和电容耦合。 它们中的至少两个是半导体，具有相反的导电性或相同类型的导电性，但是具有不同浓度的掺杂剂，并且这些掺杂物的两侧之间相互接触。 这些块在隔离区域内的相互排列，它们的导电类型及其掺杂剂的浓度形成至少一个电子模块。 一些块定义输入和输出块。

公开(公告)号：US20130223138A1

公开(公告)日：2013-08-29

申请号：US13836690

申请日：2013-03-15

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract translation: 安全存储器包括具有编程的启动状态的双稳态存储单元，以及用于响应于翻转信号翻转单元的状态的装置。 存储器可以包括用于以例如小于发射显微镜的获取时间的周期产生翻转信号的时钟。

公开(公告)号：US20130214326A1

公开(公告)日：2013-08-22

申请号：US13768730

申请日：2013-02-15

Applicant: STMICROELECTRONICS SA

Inventor： Philippe Galy ,  Nicolas Guitard ,  Thomas Benoist

IPC: H01L29/74

CPC classification number: H01L29/7424 ,  H01L27/0262 ,  H01L29/87

Abstract: A device includes, within a layer of silicon on insulator, a central semiconductor zone including a central region having a first type of conductivity, two intermediate regions having a second type of conductivity opposite to that of the first one, respectively disposed on either side of and in contact with the central region in order to form two PN junctions, two semiconductor end zones respectively disposed on either side of the central zone, each end zone comprising two end regions of opposite types of conductivity, in contact with the adjacent intermediate region, the two end regions of each end zone being mutually connected electrically in order to form the two terminals of the device.

Abstract translation: 一种器件包括在绝缘体上的硅层内的包括具有第一类型导电性的中心区域的中心半导体区域，具有与第一类型导电性相反的第二类型导电率的第二类型的中间区域分别设置在 并且与中心区域接触以形成两个PN结，两个半导体端部区域分别设置在中心区域的任一侧上，每个端部区域包括与相邻中间区域接触的相反导电类型的两个端部区域， 每个端部区域的两个端部区域相互电连接以形成装置的两个端子。