-
公开(公告)号：US12135575B2
公开(公告)日：2024-11-05
申请号：US17994654
申请日：2022-11-28
Applicant: STMicroelectronics International N.V.
Inventor： Roberta Priolo
Abstract: An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree. The delay circuit causes the state-overlap to exceed the tree propagation time.
-
公开(公告)号：US12134556B2
公开(公告)日：2024-11-05
申请号：US17534286
申请日：2021-11-23
Inventor： Enri Duqi , Lorenzo Baldo , Paolo Ferrari , Benedetto Vigna , Flavio Francesco Villa , Laura Maria Castoldi , Ilaria Gelmi
IPC: B81B7/00
Abstract: A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.
-
公开(公告)号：US20240364347A1
公开(公告)日：2024-10-31
申请号：US18623331
申请日：2024-04-01
Applicant: STMicroelectronics International N.V.
Inventor： Rupesh SINGH , Ankur BAL , Kirtiman Singh RATHORE
IPC: H03L7/00 , H03K3/037 , H03K5/1534 , H03K19/20
CPC classification number: H03L7/00 , H03K3/037 , H03K5/1534 , H03K19/20
Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.
-
公开(公告)号：US20240364336A1
公开(公告)日：2024-10-31
申请号：US18308215
申请日：2023-04-27
Applicant: STMicroelectronics International N.V.
Inventor： Giulia Colonna , Enea Dimroci
CPC classification number: H03K19/0016 , H03K19/0013
Abstract: According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate.
-
公开(公告)号：US20240356744A1
公开(公告)日：2024-10-24
申请号：US18628508
申请日：2024-04-05
Applicant: STMicroelectronics International N.V.
Inventor： Antonino Mondello , Michele Alessandro Carrano , Riccardo Condorelli
Abstract: A circuit implemented as a System-on-Chip (SOC) circuit comprising a microcontroller configured to drive one or more hard macros via a respective communication interface and a shielded bus. The microcontroller configured to transmit over the shielded bus random numbers to the hard macro. The microcontroller and the hard macro configured to use these random numbers as cryptographic shared secret for authentication. The microcontroller configured to drive via the communication interface the hard macros authenticated via the random numbers.
-
Patent Agency Ranking
公开(公告)号：US20240356549A1
公开(公告)日：2024-10-24
申请号：US18632137
申请日：2024-04-10
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek JAIN
IPC: H03K19/003 , H03K3/037
CPC classification number: H03K19/00338 , H03K3/0372 , H03K3/0375
Abstract: A radiation hardened flip-flop includes a plurality of secondary flip-flops. Each secondary flip-flop includes both a data input terminal and an alternate data input terminal. Each secondary flip-flop also includes an enable terminal that selectively enables use of the alternate data input terminal. The radiation hardened flip-flop includes an error detection circuit that detects whether an error is present in one or more of the secondary flip-flops and provides an enable signal to the enable terminals indicating the presence or absence of an error in one or more of the secondary flip-flops.
-
487.发明公开公开(公告)号：US20240355714A1
公开(公告)日：2024-10-24
申请号：US18635695
申请日：2024-04-15
Applicant: STMicroelectronics International N.V.
Inventor： Mauro MAZZOLA
IPC: H01L23/495 , H01L21/48 , H01L23/00 , H01L23/31 , H01L25/065
CPC classification number: H01L23/49548 , H01L21/4828 , H01L21/4842 , H01L23/3107 , H01L23/49503 , H01L23/49517 , H01L24/08 , H01L24/97 , H01L25/0655 , H01L2224/08245 , H01L2224/97 , H01L2924/1815
Abstract: An electrically conductive substrate has mutually opposed first and second surfaces and electrically conductive die pads and elongated electrically conductive connecting bars coupled to the electrically conductive die pads. The elongated connecting bars are configured to be cut at intermediate points along their length to provide singulated substrate portions and have distributed along their length first recesses at the first surface alternating with second recesses at the second surface. Cutting the elongated connecting bars at the intermediate points provides bar remainders extending from a distal end to an electrically conductive die pad in a singulated substrate portion. The bar remainders have a serpentine pattern with one or more offsets between their distal end exposed at the surface of the insulating encapsulation of the device package and the electrically conductive die pad.
-
公开(公告)号：US20240354056A1
公开(公告)日：2024-10-24
申请号：US18305869
申请日：2023-04-24
Applicant: STMicroelectronics International N.V.
Inventor： Pierre Gobin , Jeremy Ribeiro De Freitas
Abstract: A circuit for computing sine and cosine of an angle iteratively includes: a counter; an angle updating circuit configured to compute, for each iteration, an updated value of the angle; and a coordinate updating circuit including: a first register for storing a cosine value; a second register for storing a sine value; and a first custom floating-point adder/subtractor (CFPAS) circuit and a second CFPAS circuit having a same structure, where an output of the first register and an output of the second register are coupled to a first input terminal and a second input terminal of the first CFPAS circuit, and are coupled to a second input terminal and a first input terminal of the second CFPAS circuit, where an output of the counter is coupled to a third input terminal of the first CFPAS circuit and a third input terminal of the second CFPAS circuit.
-
公开(公告)号：US20240353562A1
公开(公告)日：2024-10-24
申请号：US18302308
申请日：2023-04-18
Applicant: STMicroelectronics International N.V.
Inventor： Yann Jean-Paul Dominique Labussiere
IPC: G01S17/894 , G01B11/22 , G01S7/4865
CPC classification number: G01S17/894 , G01B11/22 , G01S7/4865
Abstract: A method of recognizing a shape using a multizone time-of-flight (ToF) sensor includes receiving, by a processor, ToF data indicating an object located within a field of view of the multizone ToF sensor, the field of view being divided into zones. The ToF data includes signal information corresponding to each zone of the field of view of the multizone ToF sensor. The ToF data may include a two-dimensional array of zone data, each of the zone data including distance information and additional signal information. The method further includes recognizing, by the processor, the object as the shape using the signal information. Recognizing the shape may include filtering, by the processor, the ToF data through an artificial intelligence (AI) model to create AI output data and recognizing the shape using the AI output data.
-
公开(公告)号：US20240353538A1
公开(公告)日：2024-10-24
申请号：US18304589
申请日：2023-04-21
Applicant: STMicroelectronics International N.V.
Inventor： Andreas Assmann
IPC: G01S7/4865 , G01S17/894
CPC classification number: G01S7/4865 , G01S17/894
Abstract: A method of ranging using a time-of-flight (ToF) ranging system includes: receiving, by a processor, a histogram generated by a ToF imager of the ToF ranging system, where the ToF imager is configured to transmit a light pulse for ranging purpose; finding a rising edge of a pulse region in the histogram, where the pulse region corresponds to a reflected light pulse from a target; fine-tuning a location of the rising edge by performing a fitting process between the rising edge and a pre-stored high-solution rising edge; and calculating an estimate of a distance of the target by adding a pre-determined offset to a distance of the rising edge after fine-tuning the location of the rising edge.
-
-
-
-
-
-
-
-
-
Search Results
1956
records
(took 0.027 seconds)
