公开(公告)号：US20150097712A1

公开(公告)日：2015-04-09

申请号：US14050081

申请日：2013-10-09

Applicant: Fergus John DOWNEY ,  Roderick McLACHLAN

Inventor： Fergus John DOWNEY ,  Roderick McLACHLAN

IPC: H03M1/78 ,  H03M1/66

CPC classification number: H03M1/785 ,  H03M1/00 ,  H03M1/069 ,  H03M1/12 ,  H03M1/664 ,  H03M1/687 ,  H03M1/747

Abstract: A digital-to-analog converter (DAC) comprising a first section having a first plurality of current flow paths forming binary weighted values in the DAC; and a second section connected to the first section and having a second plurality of current flow paths, wherein each of the first and second plurality of current flow paths are switchable between first and second nodes, and wherein weights of one or more of the second plurality of current flow paths are notionally equal to weights of one or more of the first plurality of current flow paths so as to provide redundancy in the first section.

Abstract translation: 一种数模转换器（DAC），包括具有在DAC中形成二进制加权值的第一多个电流流路的第一部分; 以及第二部分，其连接到所述第一部分并且具有第二多个电流流动路径，其中所述第一和第二多个电流流动路径中的每一个可在第一和第二节点之间切换，并且其中所述第二多个电流流中的一个或多个的权重 电流流动路径意图等于第一多个当前流动路径中的一个或多个的权重，以便在第一部分中提供冗余。

公开(公告)号：US08947446B2

公开(公告)日：2015-02-03

申请号：US13892531

申请日：2013-05-13

Applicant: Analog Devices Technology

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thacker

IPC: G06F13/372 ,  G06K9/36 ,  G06K9/64 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，即使当处理操作转换到新的像素像素或一行像素时，仍然保持恒定的提取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。

公开(公告)号：US20150030250A1

公开(公告)日：2015-01-29

申请号：US13951193

申请日：2013-07-25

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Bijesh Poyil ,  Ramandeep Singh Kukreja ,  Anil M. Sripadarao

IPC: G06K9/48

CPC classification number: G06K9/48 ,  G06K9/4638 ,  G06T7/11 ,  G06T7/12 ,  G06T7/13 ,  G06T7/136 ,  G06T7/181 ,  G06T7/194 ,  G06T2200/28

Abstract: A method includes determining a position and length of a non-zero run in a row of a pixel map. The method also includes determining a number of neighbors for the non-zero run in a preceding row, based at least in part on the position and the length. In addition, the method includes updating a correspondence map of the non-zero run and a correspondence map of a first neighbor of the non-zero run, based at least in part on a correspondence map of a second neighbor of the non-zero run, in response to a determination that the non-zero run has at least two neighbors in the preceding row.

Abstract translation: 一种方法包括确定像素图的一行中的非零运行的位置和长度。 该方法还包括至少部分地基于位置和长度来确定前一行中的非零运行的数量的邻居。 另外，该方法至少部分地基于非零运行的第二邻居的对应关系图来更新非零运行的对应关系图和非零运行的第一邻居的对应关系图 响应于确定非零运行在前一行中具有至少两个邻居。

公开(公告)号：US20140313784A1

公开(公告)日：2014-10-23

申请号：US13868459

申请日：2013-04-23

Applicant: Bernhard STRZALKOWSKI

Inventor： Bernhard STRZALKOWSKI

IPC: H02M3/335

CPC classification number: H02M3/33584

Abstract: A transformer based isolated bi-directional DC-DC power converter may have signals for controlling power transfer in first and second directions are derived from the same side of the transformer. The converter may include a transformer, a first switching circuit, a second switching circuit, and a controller. In a first mode, the controller controls the first and second switching circuits, and power is transferred from a first side to a second side. In a second mode, the controller controls the first and second switching circuits, and power is transferred from the second side to the first side.

Abstract translation: 基于变压器的隔离双向DC-DC电力转换器可以具有用于控制第一和第二方向上的功率传输的信号从变压器的同一侧导出。 转换器可以包括变压器，第一开关电路，第二开关电路和控制器。 在第一模式中，控制器控制第一和第二开关电路，并且功率从第一侧传输到第二侧。 在第二模式中，控制器控制第一和第二开关电路，并且电力从第二侧传送到第一侧。

公开(公告)号：US08860598B2

公开(公告)日：2014-10-14

申请号：US13839972

申请日：2013-03-15

Applicant: Analog Devices Technology

Inventor： Frederick Carnegie Thompson ,  John Cullinane

IPC: H03M1/60 ,  H03M1/14

CPC classification number: H03M1/145 ,  H03M1/36 ,  H03M1/46

Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract translation: A转换器系统，包括对输入信号的第一部分进行数字化的第一转换器，第一转换器包括比较器，具有模拟第一转换器中的比较器的电路结构的电路结构的定时器，定时器接收输入 信号，其指示比较器中的操作开始;第二转换器，响应于来自定时器的输出，数字化从第一部分剩余的输入信号的第二部分;以及组合器，具有从第一数字化生成数字代码的输入， 第二部分。

公开(公告)号：US20140285249A1

公开(公告)日：2014-09-25

申请号：US13848929

申请日：2013-03-22

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Eberhard Brunner

IPC: G01R19/02

CPC classification number: G01R19/02

Abstract: A root-mean-square (RMS) detector includes detection circuitry having as an input a radio frequency signal, target voltage and a set voltage and a RMS signal as an output, and a gain stage within the detection circuitry to produce the RMS signal as an output. The gain stage provides for faster settling times of the detector.

Abstract translation: 均方根（RMS）检测器包括检测电路，其具有作为输入的射频信号，目标电压和设定电压以及RMS信号作为输出，以及检测电路内的增益级，以产生RMS信号作为 一个输出。 增益级提供检测器更快的建立时间。

公开(公告)号：US20140282349A1

公开(公告)日：2014-09-18

申请号：US14028792

申请日：2013-09-17

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Roger Feng ,  Junxiao Chen ,  Bin Shao

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F2217/78

Abstract: A method can reuse at least one pin in demultiplexing (demuxing) a voltage from a pin. The method can be used to set an accurate current limit threshold in a design for test (DFT) phase and, thus, to accurately set a trimming code of a current limiter. The method uses the property that a power MOSFET has almost a same conductive resistance at a large drain current. Thus, the current limit threshold can be set according to an accurate drain-to-source voltage Vds at a small current sink that is less than a maximum current that ATE is able to provide. An accurate voltage Vds can be measured through Kelvin sensing drain and source pins of the power MOSFET, which are connected to a current sense circuit.

Abstract translation: 一种方法可以在从引脚解复用（解调））电压时重用至少一个引脚。 该方法可用于在测试（DFT）相位的设计中设置精确的电流限制阈值，从而准确地设置限流器的修整代码。 该方法使用功率MOSFET在大漏极电流下具有几乎相同的导电电阻的性质。 因此，可以根据小于ATE能够提供的最大电流的小电流宿的准确的漏极 - 源极电压Vds来设置电流限制阈值。 可以通过连接到电流检测电路的功率MOSFET的开尔文感测漏极和源极引脚来测量精确的电压Vds。

公开(公告)号：US20140269990A1

公开(公告)日：2014-09-18

申请号：US13803797

申请日：2013-03-14

Applicant: Dong CHEN

Inventor： Dong CHEN

IPC: H04L27/36

CPC classification number: H04L27/367 ,  H03F1/3247

Abstract: An amplifier may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The predistorter may separately and independently generate a predistortion signal component for the in-phase input signal and a predistortion signal component for the quadrature input signal.

Abstract translation: 放大器可以包括接收输入信号以产生预失真信号的预失真器，接收预失真信号以产生预放大信号的第一转换器，接收前置放大信号的功率放大器，基于预放大信号和输入信号产生输出信号 ，并且第二转换器对输出信号进行采样以产生反馈信号。 预失真器可以单独和独立地产生用于同相输入信号的预失真信号分量和用于正交输入信号的预失真信号分量。

公开(公告)号：US20140266842A1

公开(公告)日：2014-09-18

申请号：US13839972

申请日：2013-03-15

Applicant: Frederick Carnegie THOMPSON ,  John CULLINANE

Inventor： Frederick Carnegie THOMPSON ,  John CULLINANE

IPC: H03M1/14

CPC classification number: H03M1/145 ,  H03M1/36 ,  H03M1/46

Abstract: A converter system, including a first converter that digitizes the a first portion of an input signal, the first converter including a comparator, a timer having a circuit structure that emulates a circuit structure of a comparator in the first converter, the timer receiving an input signal indicating commencement of operations in the comparator, a second converter that digitizes a second portion of the input signal remaining from the first portion in response to an output from the timer, and a combiner having inputs to generate a digital code from the digitized first and second portions.

Abstract translation: A转换器系统，包括对输入信号的第一部分进行数字化的第一转换器，第一转换器包括比较器，具有模拟第一转换器中的比较器的电路结构的电路结构的定时器，定时器接收输入 信号，其指示比较器中的操作开始;第二转换器，响应于来自定时器的输出，数字化从第一部分剩余的输入信号的第二部分;以及组合器，具有从第一数字化生成数字代码的输入， 第二部分。

公开(公告)号：US20140266431A1

公开(公告)日：2014-09-18

申请号：US13798561

申请日：2013-03-13

Applicant: Dong CHEN

Inventor： Dong CHEN

IPC: H03F1/32

CPC classification number: H03F1/3247 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/245 ,  H03F2201/3209 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03M1/0614 ,  H03M1/1245

Abstract: A amplifier system may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The power amplifier may produce a distortion signal at a first frequency, the second converter may sample the output signal using a timing signal with a second frequency that is lower than the first frequency to generate the feedback signal, and the predistorter, based upon the feedback signal, may predistort the predistortion signal to reduce the distortion signal at the first frequency.

Abstract translation: 放大器系统可以包括接收输入信号以产生预失真信号的预失真器，接收预失真信号以产生预放大信号的第一转换器，接收前置放大信号的功率放大器，基于预放大信号和输入产生输出信号 信号，第二转换器对输出信号进行采样以产生反馈信号。 功率放大器可以以第一频率产生失真信号，第二转换器可以使用具有低于第一频率的第二频率的定时信号对输出信号进行采样以产生反馈信号，并且预失真器基于反馈 信号，可以预失真预失真信号以减小第一频率处的失真信号。