公开(公告)号：US20100108977A1

公开(公告)日：2010-05-06

申请号：US12428628

申请日：2009-04-23

Applicant: Sung Min YOON ,  Byoung Gon Yu ,  Soon Won Jung ,  Seung Yun Lee ,  Young Sam Park ,  Joon Suk Lee

Inventor： Sung Min YOON ,  Byoung Gon Yu ,  Soon Won Jung ,  Seung Yun Lee ,  Young Sam Park ,  Joon Suk Lee

IPC: H01L45/00 ,  H01L21/768 ,  H01L21/31

CPC classification number: H01L45/1226 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: A nonvolatile programmable switch device using a phase-change memory device and a method of manufacturing the same are provided. The switch device includes a substrate, a first metal electrode layer disposed on the substrate and including a plurality of terminals, a phase-change material layer disposed on the substrate and having a self-heating channel structure, the phase-change material layer having a plurality of introduction regions electrically contacting the terminals of the first metal electrode layer and a channel region interposed between the introduction regions, an insulating layer disposed on the first metal electrode layer and the phase-change material layer, a via hole disposed on the first metal electrode layer, and a second metal electrode layer disposed to fill the via hole. The switch device performs memory operations using resistive heating of a phase-change material without an additional heater electrode, thereby minimizing thermal loss due to thermal conductivity of a metal electrode to reduce power consumption of the switch device.

Abstract translation: 提供了一种使用相变存储器件的非易失性可编程开关器件及其制造方法。 开关装置包括基板，设置在基板上的多个端子的第一金属电极层，设置在基板上并具有自加热沟道结构的相变材料层，相变材料层具有 与第一金属电极层的端子和介于导入区域之间的沟道区域电接触的多个导入区域，设置在第一金属电极层和相变材料层上的绝缘层，设置在第一金属 电极层和设置成填充通孔的第二金属电极层。 开关装置利用相变材料的电阻加热来执行存储器操作，而不需要额外的加热器电极，从而最小化由于金属电极的热导率导致的热损失，从而降低开关器件的功耗。

公开(公告)号：US20090184307A1

公开(公告)日：2009-07-23

申请号：US12240013

申请日：2008-09-29

Applicant: Sung Min YOON ,  Byoung Gon Yu ,  Seung Yun Lee ,  Young Sam Park ,  Kyu Jeong Choi ,  Nam Yeal Lee

Inventor： Sung Min YOON ,  Byoung Gon Yu ,  Seung Yun Lee ,  Young Sam Park ,  Kyu Jeong Choi ,  Nam Yeal Lee

IPC: H01L21/06 ,  H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1625

Abstract: A phase change memory device and a method of fabricating the same are provided. A phase change material layer of the phase change memory device is formed of germanium (Ge)-antimony (Sb)-Tellurium (Te)-based Ge2Sb2+xTe5 (0.12≦x≦0.32), so that the crystalline state is determined as a stable single phase, not a mixed phase of a metastable phase and a stable phase, in phase transition between crystalline and amorphous states of a phase change material, and the phase transition according to increasing temperature directly transitions to the single stable phase from the amorphous state. As a result, set operation stability and distribution characteristics of set state resistances of the phase change memory device can be significantly enhanced, and an amorphous resistance can be maintained for a long time at a high temperature, i.e., around crystallization temperature, and thus reset operation stability and rewrite operation stability of the phase change memory device can be significantly enhanced.

Abstract translation: 提供了一种相变存储器件及其制造方法。 相变存储器件的相变材料层由锗（Ge） - 锑（Sb） - 碲（Te）基Ge2Sb2 + xTe5（0.12 <= x <= 0.32）形成，从而确定晶体状态 作为稳定的单相，不是相变材料的晶态和非晶态之间的相转变中的亚稳相和稳定相的混合相，并且根据升温的相变随着温度的升高直接转变为单稳态 非晶态。 结果，可以显着提高相变存储器件的设定状态电阻的设定操作稳定性和分布特性，并且可以在高温下（即，结晶温度附近）长时间保持非晶形电阻，并因此复位 可以显着提高相变存储器件的操作稳定性和重写操作的稳定性。

公开(公告)号：US20090146128A1

公开(公告)日：2009-06-11

申请号：US12326776

申请日：2008-12-02

Applicant: Seung Yun Lee ,  Young Sam Park ,  Sung Min Yoon ,  Soon Won Jung ,  Byoung Gon Yu

Inventor： Seung Yun Lee ,  Young Sam Park ,  Sung Min Yoon ,  Soon Won Jung ,  Byoung Gon Yu

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1666

Abstract: Provided are a nonvolatile memory device and a method of fabricating the same, in which a phase-change layer is formed using a solid-state reaction to reduce a programmable volume, thereby lessening power consumption. The device includes a first reactant layer, a second reactant layer formed on the first reactant layer, and a phase-change layer formed between the first and second reactant layers due to a solid-state reaction between a material forming the first reactant layer and a material forming the second reactant layer. The phase-change memory device consumes low power and operates at high speed.

Abstract translation: 提供了一种非易失性存储器件及其制造方法，其中使用固态反应形成相变层以减少可编程体积，从而降低功耗。 该装置包括第一反应物层，形成在第一反应物层上的第二反应物层和由形成第一反应物层的材料与第一反应物层之间的固态反应形成在第一和第二反应物层之间的相变层 形成第二反应物层的材料。 相变存储器件消耗低功率并以高速运行。

公开(公告)号：US20090140148A1

公开(公告)日：2009-06-04

申请号：US12181893

申请日：2008-07-29

Applicant: Woo Seok Yang ,  Seong Mok Cho ,  Ho Jun Ryu ,  Sang Hoon Cheon ,  Byoung Gon Yu ,  Chang Auck Choi

Inventor： Woo Seok Yang ,  Seong Mok Cho ,  Ho Jun Ryu ,  Sang Hoon Cheon ,  Byoung Gon Yu ,  Chang Auck Choi

IPC: H01L27/14 ,  H01L21/00

CPC classification number: G01J5/20

Abstract: A bolometer having decreased noise and increased temperature sensitivity and a method of manufacturing the same are provided. The bolometer has a resistive layer formed of single crystalline silicon (Si) or silicon germanium (Si1-xGex, x=0.2˜0.5) having high crystallinity, such that 1/f noise can be reduced and temperature sensitivity can be significantly improved compared to a conventional amorphous silicon bolometer.

Abstract translation: 提供了具有降低的噪声和增加的温度敏感度的辐射热量计及其制造方法。 测辐射热计具有由具有高结晶度的单晶硅（Si）或硅锗（Si1-xGex，x = 0.2〜0.5）形成的电阻层，使得1 / f噪声可以降低，并且与 一种常规的非晶硅测辐射热计。

公开(公告)号：US07335945B2

公开(公告)日：2008-02-26

申请号：US11012695

申请日：2004-12-16

Applicant: Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

Inventor： Dae Woo Lee ,  Tae Moon Roh ,  Sung Ku Kwon ,  Il Yong Park ,  Yil Suk Yang ,  Byoung Gon Yu ,  Jong Dae Kim

IPC: H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78645

Abstract: Provided are a multi-gate MOS transistor and a method of manufacturing the same. Two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin are used as a channel. Therefore, a channel width is increased, so that current driving capability of a device is improved, and high performance nano-level semiconductor IC and highly integrated memory IC can be manufactured through the optimization and stability of a process.

Abstract translation: 提供一种多栅极MOS晶体管及其制造方法。 垂直堆叠在硅绝缘体（SOI）基板上的两个硅散热片，上硅片的四个侧表面和下硅片的三个侧表面用作通道。 因此，通道宽度增加，从而提高了器件的电流驱动能力，并且可以通过工艺的优化和稳定性来制造高性能纳米级半导体IC和高度集成的存储器IC。

公开(公告)号：US20070173010A1

公开(公告)日：2007-07-26

申请号：US11633216

申请日：2006-12-04

Applicant: Seung-Yun Lee ,  Sangouk Ryu ,  Sung Yoon ,  Young Park ,  Kyu-Jeong Choi ,  Nam-Yeal Lee ,  Byoung-Gon Yu

Inventor： Seung-Yun Lee ,  Sangouk Ryu ,  Sung Yoon ,  Young Park ,  Kyu-Jeong Choi ,  Nam-Yeal Lee ,  Byoung-Gon Yu

IPC: G11C19/08 ,  H01L21/8249 ,  H01L31/00 ,  H01L31/117

CPC classification number: H01L27/0635 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008 ,  G11C2213/79 ,  H01L21/8249 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  Y10S438/947

Abstract: An embedded memory required for a high performance, multifunction SOC, and a method of fabricating the same are provided. The memory includes a bipolar transistor, a phase-change memory device and a MOS transistor, adjacent and electrically connected, on a substrate. The bipolar transistor includes a base composed of SiGe disposed on a collector. The phase-change memory device has a phase-change material layer which is changed from an amorphous state to a crystalline state by a current, and a heating layer composed of SiGe that contacts the lower surface of the phase-change material layer.

Abstract translation: 提供了高性能多功能SOC所需的嵌入式存储器及其制造方法。 存储器包括在衬底上相邻并电连接的双极晶体管，相变存储器件和MOS晶体管。 双极晶体管包括由设置在集电极上的SiGe组成的基极。 相变存储器件具有通过电流从非晶状态转变为结晶态的相变材料层和由与相变材料层的下表面接触的SiGe构成的加热层。

公开(公告)号：US06759714B2

公开(公告)日：2004-07-06

申请号：US10322232

申请日：2002-12-17

Applicant: Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

Inventor： Sang Gi Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  II-Young Park ,  Byoung-Gon Yu ,  Jong Dae Kim

IPC: H01L2972

CPC classification number: H01L21/76289 ,  H01L21/84 ,  H01L23/367 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor fabrication technology; and, more particularly, to a semiconductor device having a heat release structure that uses a silicon-on-insulator (SOI) substrate, and a method for fabricating the semiconductor device. The device and method of the present research provides a semiconductor device having a high heat-release structure and high heat-release structure, and a fabrication method thereof. In the research, the heat and high-frequency noises that are generated in the integrated circuit are released outside of the substrate through the tunneling region quickly by forming an integrated circuit on a silicon-on-insulator (SOI) substrate, aiid removing a buried insulation layer under the integrated circuit to form a tunneling region. The heat-release efficiency can be enhanced much more, when unevenness is formed on the surfaces of the upper and lower parts of the tunneling region, or when the air or other gases having excellent heat conductivity is flown into the tunneling region.

Abstract translation: 提供半导体制造技术; 更具体地说，涉及具有使用绝缘体上硅（SOI）衬底的散热结构的半导体器件，以及制造半导体器件的方法。 本研究的装置和方法提供了具有高散热结构和高放热结构的半导体器件及其制造方法。 在研究中，通过在绝缘体上硅（SOI）衬底上形成集成电路，快速地通过隧道区域在衬底外部释放集成电路中产生的热和高频噪声，除去埋入 集成电路下的绝缘层形成隧道区。 当在隧道区域的上部和下部的表面上形成不均匀时，或者当具有优良导热性的空气或其它气体流入隧道区域时，可以进一步提高散热效率。

公开(公告)号：US08558295B2

公开(公告)日：2013-10-15

申请号：US12838878

申请日：2010-07-19

Applicant: Sung Min Yoon ,  Chun Won Byun ,  Shin Hyuk Yang ,  Sang Hee Park ,  Soon Won Jung ,  Seung Youl Kang ,  Chi Sun Hwang ,  Byoung Gon Yu

Inventor： Sung Min Yoon ,  Chun Won Byun ,  Shin Hyuk Yang ,  Sang Hee Park ,  Soon Won Jung ,  Seung Youl Kang ,  Chi Sun Hwang ,  Byoung Gon Yu

IPC: H01G7/06

CPC classification number: H01L29/6684 ,  B82Y10/00 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/78391

Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.

Abstract translation: 提供一种非易失性存储单元及其制造方法。 非易失性存储单元包括存储晶体管和驱动晶体管。 存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。 驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。 存储晶体管和驱动晶体管设置在同一衬底上。 非易失性存储单元在可见光区域是透明的。

公开(公告)号：US08476106B2

公开(公告)日：2013-07-02

申请号：US13469558

申请日：2012-05-11

Applicant: Sung Min Yoon ,  Shin Hyuk Yang ,  Soon Won Jung ,  Seung Youl Kang ,  Doo Hee Cho ,  Chun Won Byun ,  Chi Sun Hwang ,  Byoung Gon Yu ,  Kyoung Ik Cho

Inventor： Sung Min Yoon ,  Shin Hyuk Yang ,  Soon Won Jung ,  Seung Youl Kang ,  Doo Hee Cho ,  Chun Won Byun ,  Chi Sun Hwang ,  Byoung Gon Yu ,  Kyoung Ik Cho

IPC: H01L51/40

CPC classification number: H01L21/28291 ,  H01L29/78391 ,  H01L29/7869

Abstract: Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process.

Abstract translation: 提供了一种透明非易失性存储器薄膜晶体管（TFT）及其制造方法。 存储TFT包括设置在透明基板上的源极和漏极。 透明半导体薄层设置在源电极和漏电极之间，并且透明基板设置在源极和漏极之间。 有机铁电薄层设置在透明半导体薄层上。 栅电极与透明半导体薄层对准地设置在有机铁电薄层上。 因此，透明非易失性存储器TFT采用有机铁电薄层，氧化物半导体薄层和设置在有机铁电薄层之上和之下的辅助绝缘层，从而能够低成本地制造能够低的透明非易失性存储器件 温度过程。

公开(公告)号：US20130149803A1

公开(公告)日：2013-06-13

申请号：US13606127

申请日：2012-09-07

Applicant: Jaehyun MOON ,  Jeong Ik Lee ,  Doo-Hee Cho ,  Seung Koo Park ,  Hye Yong Chu ,  Joo Hyun Hwang ,  Jin Wook Shin ,  Jun-Han Han ,  Chul Woong Joo ,  Jin Woo Huh ,  Byoung Gon Yu

Inventor： Jaehyun MOON ,  Jeong Ik Lee ,  Doo-Hee Cho ,  Seung Koo Park ,  Hye Yong Chu ,  Joo Hyun Hwang ,  Jin Wook Shin ,  Jun-Han Han ,  Chul Woong Joo ,  Jin Woo Huh ,  Byoung Gon Yu

IPC: H01L51/56

CPC classification number: H01L51/5268

Abstract: Provided is a method of fabricating an organic light emitting diode. The method may include preparing a substrate, forming a textured portion on the substrate, the textured portion including protruding patterns randomly and irregularly arranged on the substrate, forming a planarization layer on the substrate to planarize the substrate formed with the textured portion, forming a first electrode on the planarization layer, forming an organic light emitting layer on the first electrode, and forming a second electrode on the organic light emitting layer.

Abstract translation: 提供一种制造有机发光二极管的方法。 该方法可以包括制备衬底，在衬底上形成纹理化部分，纹理化部分包括随机和不规则地布置在衬底上的突出图案，在衬底上形成平坦化层，以平坦化形成有纹理部分的衬底，形成第一 在所述平坦化层上形成有机发光层，在所述有机发光层上形成第二电极。