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51 条记录 (耗时 0.022 秒)

    KEYPAD ASSEMBLY FOR PORTABLE TERMINAL
    41.
    发明申请
    KEYPAD ASSEMBLY FOR PORTABLE TERMINAL 有权
    便携式终端用键盘组件

    公开(公告)号：US20120138441A1

    公开(公告)日：2012-06-07

    申请号：US13117268

    申请日：2011-05-27

    申请人： Byung-Sun KIM ,  Min-Su JUNG ,  Cheol-Hee KIM

    发明人： Byung-Sun KIM ,  Min-Su JUNG ,  Cheol-Hee KIM

    IPC分类号： H01H13/76

    CPC分类号： H01H13/705 ,  H01H2221/056 ,  H01H2223/036 ,  H01H2231/022 ,  H01H2233/03 ,  H04M1/23

    摘要： A keypad assembly includes an operation member deformed according to user's manipulation to operate key switches, a binding member disposed on a top surface of the operation member, binding pieces extending and bent from the binding member to enclose sides of the operation member on an edge of the binding member, and a manipulation member disposed on a top surface of the binding member, the manipulation member including at least one key tops, in which the binding members are bound onto inner side walls of a housing of the portable terminal.

    摘要翻译： 键盘组件包括根据用户的操纵而变形以操作键开关的操作构件，设置在操作构件的顶表面上的装订构件，从装订构件延伸和弯曲的绑定件，以将操作构件的侧面包围在操作构件的边缘上 装订构件和设置在装订构件的顶表面上的操纵构件，操纵构件包括至少一个键顶，其中装订构件被绑定到便携式终端的壳体的内侧壁上。

    Semiconductor device having electrostatic discharge protection circuit and method of manufacturing the same
    42.
    发明授权
    Semiconductor device having electrostatic discharge protection circuit and method of manufacturing the same 有权
    具有静电放电保护电路的半导体装置及其制造方法

    公开(公告)号：US08143690B2

    公开(公告)日：2012-03-27

    申请号：US12219336

    申请日：2008-07-21

    申请人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

    发明人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0814 ,  H01L27/0255

    摘要： Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

    摘要翻译： 提供具有片上型静电放电（ESD）保护电路的半导体器件及其制造方法。 片上型ESD保护电路可以包括具有与半导体衬底中的第二导电类型区域接触的第一导电类型区域的第一结二极管和具有布置在第一导电类型区域上并与第一导电类型区域接触的金属材料层的第一肖特基二极管 的半导体衬底。

    Device and Method for Hierarchical Broadcasting
    43.
    发明申请
    Device and Method for Hierarchical Broadcasting 有权
    分层广播的设备和方法

    公开(公告)号：US20120042333A1

    公开(公告)日：2012-02-16

    申请号：US13255491

    申请日：2010-03-16

    申请人： Keunsik Lee ,  Byung Sun Kim ,  Chang-Seob Park ,  Sang-Jin Hahm ,  In-Joon Cho

    发明人： Keunsik Lee ,  Byung Sun Kim ,  Chang-Seob Park ,  Sang-Jin Hahm ,  In-Joon Cho

    IPC分类号： H04N7/16 ,  H04N7/167

    CPC分类号： H04H20/33 ,  H04H20/18 ,  H04H20/423 ,  H04N19/30

    摘要： A hierarchical broadcasting device and method are disclosed. In the hierarchical broadcasting method, a broadcast transmitting device may transmit lower layer broadcast data for an existing broadcast to a broadcast receiving device via a first communication network, and may transmit upper layer broadcast data for an improved broadcast to the broadcast receiving device via a second communication network. In this instance, the broadcast receiving device combines the lower layer broadcast data and the upper layer broadcast data in order to display the improved broadcast.

    摘要翻译： 公开了分级广播设备和方法。 在分层广播方法中，广播发送装置可以经由第一通信网络向广播接收装置发送现有广播的下层广播数据，并且可以经由第二通信网络向广播接收装置发送用于改进的广播的上层广播数据 通讯网络 在这种情况下，广播接收装置组合下层广播数据和上层广播数据，以便显示改进的广播。

    Method for fabricating cell structure of non-volatile memory device
    47.
    发明授权
    Method for fabricating cell structure of non-volatile memory device 失效
    非易失性存储器件单元结构的制造方法

    公开(公告)号：US07445992B2

    公开(公告)日：2008-11-04

    申请号：US11281471

    申请日：2005-11-18

    申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

    摘要： A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

    摘要翻译： 使用氮化物层作为浮动栅极隔离物的非易失性存储器件的单元结构包括形成在半导体衬底上的栅极堆叠和浮置栅极晶体管。 栅极堆叠包括浮置栅极的第一部分，形成在浮置栅极的第一部分上的控制栅极以及与浮动栅极的第一部分的侧壁相邻的非氮化物间隔物。 浮栅晶体管包括浮置栅极的第二部分，其基本上与衬底中形成的源极和/或漏极重叠。 将紫外线施加到编程单元的非氮化物间隔物可能导致浮栅的第二部分放电，从而容易地擦除编程的单元。

    Semiconductor memory device supporting two data ports
    48.
    发明授权
    Semiconductor memory device supporting two data ports 有权
    半导体存储器件支持两个数据端口

    公开(公告)号：US06885609B2

    公开(公告)日：2005-04-26

    申请号：US10724687

    申请日：2003-12-02

    申请人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

    发明人： Tae-jung Lee ,  Byung-sun Kim ,  Joon-hyung Lee

    IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C8/00 ,  G11C11/00

    CPC分类号： G11C8/16

    摘要： A layout of a memory cell of a dual-port semiconductor memory device provides for one memory cell that includes a total of eight transistors, including two NMOS scan transistors. Among the transistors, two PMOS transistors and six NMOS transistors are disposed in one N-well area and one contiguous P-well area of a semiconductor substrate, respectively. The N-well area is disposed at a corner of the memory cell for improving efficiency of the layout. Since one N-well area and one P-well area are formed in the semiconductor substrate, the size of an isolated area between the N-well area and the P-well area can be reduced, thus also reducing the size of a memory cell.

    摘要翻译： 双端口半导体存储器件的存储单元的布局提供了一个存储单元，其包括总共八个晶体管，包括两个NMOS扫描晶体管。 在晶体管中，两个PMOS晶体管和六个NMOS晶体管分别设置在半导体衬底的一个N阱区域和一个邻接的P阱区域中。 N阱区域设置在存储单元的拐角处，以提高布局的效率。 由于在半导体衬底中形成一个N阱区和一个P阱区，所以可以减小N阱区和P阱区之间的隔离区的大小，从而也减小了存储单元的尺寸 。

    Semiconductor device having silicon on insulator and fabricating method therefor
    49.
    发明授权
    Semiconductor device having silicon on insulator and fabricating method therefor 有权
    具有硅绝缘体的半导体器件及其制造方法

    公开(公告)号：US06693325B1

    公开(公告)日：2004-02-17

    申请号：US09640851

    申请日：2000-08-17

    申请人： Young-Gun Ko ,  Byung-Sun Kim

    发明人： Young-Gun Ko ,  Byung-Sun Kim

    IPC分类号： H01L2712

    CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

    摘要： The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer. A first groove is formed between the STI at one side of the transistor by etching the surface silicon layer and insulating layer to expose a predetermined portion of an active region of a second conductivity type well in the semiconductor substrate. A second groove is formed between the STI at one side of the first groove by etching the surface silicon layer and insulating layer to expose a predetermined portion of the active region of the semiconductor substrate. A first diode diffusion region of a first conductivity type is formed in a second conductivity type well under the first groove, and a second diode diffusion region of a second conductivity type is formed in the semiconductor substrate under the second groove.

    摘要翻译： 本发明涉及一种高度集成的SOI半导体器件以及通过减小二极管或阱电阻之间的距离而不会降低绝缘特性来制造SOI半导体器件的方法。 该器件包括第一导电型半导体衬底和通过在半导体衬底上插入绝缘层而形成的表面硅层。 通过蚀刻表面硅层，绝缘层和衬底的预定部分以暴露用于元件分离区域的半导体衬底的一部分而形成沟槽，并且在沟槽中形成STI。 晶体管构造在被绝缘层包围的表面硅层上，STI与栅电极位于其中心，源/漏区形成在栅电极的两个边缘的表面硅层中，以使其底部 部分与绝缘层接触。 通过蚀刻表面硅层和绝缘层，在晶体管的一侧的STI之间形成第一凹槽，以暴露半导体衬底中阱的第二导电类型的有源区的预定部分。 通过蚀刻表面硅层和绝缘层，在第一凹槽的一侧的STI之间形成第二凹槽，以露出半导体衬底的有源区的预定部分。 第一导电类型的第一二极管扩散区形成在第一沟槽下面的第二导电类型阱中，并且在第二沟槽下面的半导体衬底中形成第二导电类型的第二二极管扩散区。

    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
    50.
    发明授权
    SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same 有权
    用于消除SOI MOSFET中的浮体效应的SOI半导体集成电路及其制造方法

    公开(公告)号：US06498370B1

    公开(公告)日：2002-12-24

    申请号：US09695341

    申请日：2000-10-24

    申请人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

    发明人： Young-Wug Kim ,  Byung-Sun Kim ,  Hee-Sung Kang ,  Young-Gun Ko ,  Sung-Bae Park

    IPC分类号： H01L2701

    CPC分类号： H01L29/78615

    摘要： A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

    摘要翻译： 提供绝缘体上硅（SOD集成电路和制造SOI集成电路的方法），在SOI衬底上形成至少一个隔离晶体管有源区和体线，晶体管有源区和体线被包围 通过与SOI衬底的埋置绝缘层接触的隔离层，将晶体管有源区的侧壁的一部分延伸到体线，由此，晶体管有源区域通过a 主体延伸部由主体绝缘层覆盖，在晶体管有源区域上形成绝缘栅极图案，栅极图案的一端与主体绝缘层重叠。