公开(公告)号：US20070275538A1

公开(公告)日：2007-11-29

申请号：US11539612

申请日：2006-10-06

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract translation: 提供了一种用于半导体器件的STI间隙填充处理的方法。 在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。 此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。 该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。 此外，该方法包括用第一氧化物将沟槽填充到第一深度。 使用旋涂工艺填充第一氧化物。 该方法还包括对沟槽内的第一氧化物进行第一致密化处理。 另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。 该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

公开(公告)号：US06649517B2

公开(公告)日：2003-11-18

申请号：US09859353

申请日：2001-05-18

Applicant: Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

Inventor： Young-Way Teh ,  Victor Seng Keong Lim ,  Ting Cheong Ang

IPC: H01L214763

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76804 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Abstract translation: 提供了一种新的方法和结构来创建互连线。 在与互连线的纵向方向垂直的平面中截取的本发明的互连线的横截面是与传统的互连线的矩形或矩形横截面相反的三角形。

公开(公告)号：US06611024B2

公开(公告)日：2003-08-26

申请号：US09946981

申请日：2001-09-06

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC: H01L2701

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

公开(公告)号：US06465296B1

公开(公告)日：2002-10-15

申请号：US10167095

申请日：2002-06-10

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

IPC: H01L218238

CPC classification number: H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

Abstract: A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

Abstract translation: 提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。 暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。 然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

公开(公告)号：US06406994B1

公开(公告)日：2002-06-18

申请号：US09726657

申请日：2000-11-30

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

IPC: H01L2144

CPC classification number: B41M5/5254 ,  B41M5/508 ,  B41M5/5218 ,  B41M5/5272 ,  Y10T428/24802

Abstract: A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.

Abstract translation: 描述了三层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 第一类型的第一介电层沉积在绝缘层上。 第二类型的第二介电层沉积在第一介电层上。 通孔图案被蚀刻到第二介电层中。 此后，第一类型的第三电介质层沉积在图案化的第二介电层上。 同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。 如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。 如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

公开(公告)号：US06406975B1

公开(公告)日：2002-06-18

申请号：US09721718

申请日：2000-11-27

Applicant: Victor Seng Keong Lim ,  Young-Way Teh ,  Ting-Cheong Ang ,  Alex See ,  Yong Kong Siew

Inventor： Victor Seng Keong Lim ,  Young-Way Teh ,  Ting-Cheong Ang ,  Alex See ,  Yong Kong Siew

IPC: H01L2176

CPC classification number: H01L21/764 ,  H01L21/76232

Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.

Abstract translation: 制造具有气隙的浅沟槽隔离（STI）的方法，该气隙是通过将有机填充材料分解成盖层形成的。 衬底层和阻挡层形成在衬底上。 衬垫层和阻挡层被图案化以形成沟槽开口。 我们通过蚀刻通过沟槽开口在衬底中形成沟槽。 第一衬里层形成在沟槽的侧壁上。 在阻挡层和第一衬里层上的第二衬里层。 在第二衬垫层上形成填充材料以填充沟槽。 在重要的步骤中，覆盖层沉积在填充材料和第二衬里层上。 对填充材料进行等离子体处理并加热以使填充材料汽化，使得填充材料通过盖层扩散以形成间隙。 绝缘层沉积在覆盖层上。 绝缘层被平坦化。 去除阻挡层。

公开(公告)号：US06380106B1

公开(公告)日：2002-04-30

申请号：US09721719

申请日：2000-11-27

Applicant: Seng Keong Victor Lim ,  Young-way Teh ,  Ting-Cheong Ang ,  Alex See ,  Yong Kong Siew

Inventor： Seng Keong Victor Lim ,  Young-way Teh ,  Ting-Cheong Ang ,  Alex See ,  Yong Kong Siew

IPC: H01L2131

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/7682

Abstract: A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol (PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. In another critical step, we vaporize the filler material changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. An insulating layer is formed over the permeable dielectric layer.

Abstract translation: 一种制造具有通过汽化填料聚合物材料形成气隙的金属化方案的方法。 填充材料被临界可渗透的介电层覆盖。 该方法开始于在半导体结构上形成间隔的导线。 间隔的导线具有顶表面。 在间隔的导线和半导体结构之上形成填充材料。 填充材料优选由选自聚丙二醇（PPG），聚丁二烯（PB）聚乙二醇（PEG），氟化无定形碳和聚己内酯二醇（PCL）组成的组中的材料组成，并且通过旋涂工艺或 CVD工艺。 我们回蚀填充材料以暴露间隔的导线的顶表面。 接下来，将半导体结构加载到HDPCVD室中。 在关键步骤中，在填充材料上形成可渗透介电层。 可渗透介电层具有允许分解的气相填充材料扩散通过的性质。 在另一个关键步骤中，我们将填充材料蒸发成将填料材料变成气相填料。 气相填充材料通过可渗透的介电层扩散以在间隔的导线之间形成间隙。 在可渗透介电层上形成绝缘层。

公开(公告)号：US08110502B2

公开(公告)日：2012-02-07

申请号：US11394529

申请日：2006-03-30

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/7685 ,  H01L21/76862

Abstract: A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma environment to facilitate adhesion between the diffusion barrier layer and the dielectric layer at an interface region. Also, the method includes processing the semiconductor substrate while maintaining attachment between the dielectric layer and the diffusion barrier layer at the interface region. The subjecting the diffusion barrier layer to a plasma environment includes maintaining a thickness of the barrier diffusion layer.

Abstract translation: 提供一种制造半导体器件的方法。 在具体实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括形成覆盖表面区域并形成覆盖在电介质层上的扩散阻挡层的电介质层。 此外，该方法包括使扩散阻挡层经受等离子体环境以促进在界面区域处的扩散阻挡层和电介质层之间的粘附。 此外，该方法包括处理半导体衬底，同时保持介电层和界面区域处的扩散阻挡层之间的附着。 将扩散阻挡层经受等离子体环境包括保持阻挡扩散层的厚度。

公开(公告)号：US08026151B2

公开(公告)日：2011-09-27

申请号：US12273323

申请日：2008-11-18

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/00

CPC classification number: H01L21/76224

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract translation: 提供了一种用于半导体器件的STI间隙填充处理的方法。 在本发明的具体实施方案中，该方法包括形成覆盖衬底的阻挡层。 此外，该方法包括在衬底内形成沟槽，其中沟槽具有侧壁，底部和深度。 该方法还包括在沟槽内形成衬垫，衬垫衬在沟槽的侧壁和底部。 此外，该方法包括用第一氧化物将沟槽填充到第一深度。 使用旋涂工艺填充第一氧化物。 该方法还包括对沟槽内的第一氧化物进行第一致密化处理。 另外，该方法包括使用HDP工艺在沟槽内沉积第二氧化物以填充至少整个沟槽。 该方法还包括对沟槽内的第一和第二氧化物进行第二致密化处理。

公开(公告)号：US07910475B2

公开(公告)日：2011-03-22

申请号：US12505414

申请日：2009-07-17

Applicant: Ting Cheong Ang

Inventor： Ting Cheong Ang

IPC: H01L21/00

CPC classification number: H01L21/02131 ,  C23C16/30 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31604 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract translation: 提供一种形成半导体器件的方法。 在一个实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括沉积覆盖表面区域的介电层。 介电层通过CVD工艺形成。 此外，该方法包括形成覆盖在电介质层上的扩散阻挡层。 此外，该方法包括形成覆盖扩散阻挡层的导电层。 另外，该方法包括使用化学机械抛光工艺来减小导电层的厚度。 CVD工艺利用氟作为反应物形成电介质层。 此外，介电层与等于或小于3.3的介电常数相关联。