Abstract:
A circuit of a scanner to perform a color space conversion on an RGB signal. The circuit has several sampling-amplified-offset devices to sample, amplify and compensate potential of an R charge signal, a G charge signal and a B charge signal to obtain an R analog signal, a G analog signal and a B analog signal. The circuit further has a gain adder to multiply the corresponding weighted gain with the R analog signal, the G analog signal and the B analog signal. The multiplication results are then summed up to obtain an addition analog signal. A multiplexer is also included to select between the R analog signal, the G analog signal, the B analog signal and the addition analog signal for output.
Abstract:
A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating system is used for receiving values input by the users, and for calculating parameters of the MOSFET according to the input values. The parameter calculating system includes a type selecting module (110), a value receiving module (120), a number determining module (130), a parameter calculating module (140), and a circuit netlist generating module (150). A related method is also disclosed.
Abstract:
A circuit board indicator comprises a plurality of lamps with cut and bent terminals, an outer plastic holder and an inner plastic holder. The outer plastic holder contains an accommodating chamber, which has a plurality of rounded holes on a lateral side thereof. The inner plastic holder has a plurality of positioning recesses and each of the positioning recesses has a guiding slot on topside thereof. The terminals of the lamps are guided by the guiding slot and inserted into corresponding positioning recesses. The inner plastic holder further has a plurality of clamping dents to clamp corresponding lamps. The inner plastic holder has barbs on two lateral sides thereof and corresponding to rectangular grooves on the outer plastic holder. The barbs are engaged into corresponding rectangular grooves when the inner plastic holder is assembled to the outer plastic holder.
Abstract:
An electronic device reads a layout file of a printed circuit board (PCB) to be manufactured from a storage device, obtains length information and section area information of copper cladding distributed on power source areas and ground trace areas in each of one or more layers of the PCB to be manufactured by analyzing the layout file, and calculates power loss in each of the one or more layers according to the length information, the section area information, a resistance value of the copper cladding, and preset parameters of a power supply module and an integrated circuit (IC) load to be located on the PCB. In response to a determination that the power loss in the layer exceeds a preset range, the electronic device indicates the locations of the power source areas and the ground trace areas of a layer in the PCB layout file which need to be redesigned.
Abstract:
In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.
Abstract:
A printed circuit board (PCB) comprising a first circuit area, a second circuit area, a plurality of connecting elements, and a plurality of connecting terminals placed on the first circuit area, wherein the first circuit area are electrically connected to the second circuit area through the plurality of connecting elements, the plurality of connecting elements are arranged in sequence to extend toward the plurality of connecting terminals, to form shortest current paths from the second circuit area via corresponding one of the connecting elements to the connecting terminals, respectively, and each shortest current path between the corresponding one of the connecting elements and the corresponding one of the connecting terminals is uncoated with conductive material.
Abstract:
A system for optimizing a current overload protection circuit includes an input device, a data storage device, a central processing device, and a display. The central processing device includes a storage module, a control module, and a calculation module. The storage module stores a VI application therein. The control module receives instructions from the input device and selects virtual electronic components of the current overload protection circuit from the data storage device and connection of the selected electronic components. The current overload protection circuit is completed and run in the VI application; electronic components significantly affecting the maximum protection current are labeled. The calculation module calculates normal distribution samples of the current overload protection circuit based on the labeled electronic components. The display shows whether the current overload protection circuit meets a process capability standard.
Abstract:
The present disclosure illustrates a feedforward controlled envelope modulator and a feedforward control circuit thereof. The feedforward controlled envelope modulator comprises a linear amplifier circuit, a switching amplifier, and a feedforward control circuit. The linear amplifier circuit amplifies an input voltage signal, so as to output an output voltage signal to a load node. The switching amplifier receives a comparison signal, and outputs a switching current to the load node according to the comparison signal. The feedforward control circuit comprises a duplicate linear amplifier circuit and a hysteresis comparator. The duplicate linear amplifier circuit amplifies the input voltage signal, so as to output a reference voltage signal, wherein an amplifying gain of the duplicate linear amplifier circuit is identical to an amplifying gain of the linear amplifier circuit. The hysteresis comparator compares the output voltage signal and the reference voltage signal, so as to output the comparison signal.
Abstract:
A printed circuit board includes a plurality of power layers. Each power layer defining a number of vias arranged in a number of rows. The number of the power layers is N (N>3). The power layers are defined as a 1st, 2nd, . . . , Nth power layer. The vias of the 1st power layer are connected to other power layers by a step-shaped connection means.
Abstract:
A phase modulation method with a polar transmitter. A target frequency is first designated by comparing the RF signal with a reference frequency and the phase sample. An oscillator control word is generated based on the target frequency. A digital oscillator can modulate from a first phase to a second phase to synthesize a preliminary RF signal based on the oscillator control word. When the target frequency exceeds the modulation capability of the digital oscillator, the oscillator control word is generated based on the target frequency minus 180 degrees, and the preliminary RF signal is shifted by 180 degrees to be the RF signal having the target frequency. When the target frequency does not exceed the modulation capability of the digital oscillator, the oscillator control word is generated solely based on the target frequency to output the preliminary RF signal to be the RF signal having the target frequency.