利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

56 条记录 (耗时 0.022 秒)

    On-chip frequency degradation compensation
    41.
    发明授权
    On-chip frequency degradation compensation 失效
    片上频率降级补偿

    公开(公告)号：US07501845B2

    公开(公告)日：2009-03-10

    申请号：US12082065

    申请日：2008-04-07

    申请人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    发明人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    IPC分类号： G01R31/26

    CPC分类号： G06F1/04

    摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

    摘要翻译： 本发明的实施例包括三个可靠性振荡器。 在一个实施例中，片上频率补偿电路包括有选择地启用的可靠性振荡器以产生参考振荡信号，时钟可靠性振荡器以产生AC降级振荡信号，以及静态可靠性振荡器以产生DC偏压降级振荡信号。 耦合到可靠性振荡器的比较电路比较振荡信号，并且如果比较确定频率劣化大于预定阈值，则产生频率补偿信号。

    On-chip frequency degradation compensation
    42.
    发明申请
    On-chip frequency degradation compensation 失效

    公开(公告)号：US20080252329A1

    公开(公告)日：2008-10-16

    申请号：US12082065

    申请日：2008-04-07

    申请人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    发明人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    IPC分类号： G01R31/26

    CPC分类号： G06F1/04

    摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

    On-chip frequency degradation compensation
    44.
    发明授权
    On-chip frequency degradation compensation 有权
    片上频率降级补偿

    公开(公告)号：US07394274B2

    公开(公告)日：2008-07-01

    申请号：US11879645

    申请日：2007-07-17

    申请人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    发明人： Ravisangar Muniandy ,  Gregory F. Taylor ,  Payman Aminzadeh

    IPC分类号： G01R31/26

    CPC分类号： G06F1/04

    摘要： Embodiments of the invention include a trio of reliability oscillators. In one embodiment, an on-chip frequency compensation circuit includes a selectively enabled reliability oscillator to generate a reference oscillating signal, a clocked reliability oscillator to generate an AC degraded oscillating signal, and a static reliability oscillator to generate a DC bias degraded oscillating signal. A compare circuit coupled to the reliability oscillators compares the oscillating signals and generates a frequency compensation signal if the comparison determines that there is frequency degradation greater than a predetermined threshold.

    摘要翻译： 本发明的实施例包括三个可靠性振荡器。 在一个实施例中，片上频率补偿电路包括有选择地启用的可靠性振荡器以产生参考振荡信号，时钟可靠性振荡器以产生AC降级振荡信号，以及静态可靠性振荡器以产生DC偏压降级振荡信号。 耦合到可靠性振荡器的比较电路比较振荡信号，并且如果比较确定频率劣化大于预定阈值，则产生频率补偿信号。

    Method and apparatus to ensure proper voltage and frequency configuration signals are defined before applying power to processor
    47.
    发明授权
    Method and apparatus to ensure proper voltage and frequency configuration signals are defined before applying power to processor 失效
    在对处理器施加电力之前，确定了确定正确的电压和频率配置信号的方法和装置

    公开(公告)号：US06874083B2

    公开(公告)日：2005-03-29

    申请号：US09746168

    申请日：2000-12-22

    申请人： Ananda Sarangi ,  Rachael Jade Parker ,  Edward P. Osburn ,  Gregory F. Taylor

    发明人： Ananda Sarangi ,  Rachael Jade Parker ,  Edward P. Osburn ,  Gregory F. Taylor

    IPC分类号： G06F1/24 ,  G06F1/32

    CPC分类号： G06F1/24

    摘要： A dynamic processor configuration and power-up programs a processor's fuse block with configuration signals during processor manufacturing. The processor configuration signals include a core voltage identifier and a system bus frequency identifier. When power is applied to the platform, a control signal is used to prevent power-up of the platform's processor related circuitry. While the platform awaits full power-up, the fuse block is powered up. When the fuse block is powered up, the control signal is used to allow the configuration signals to be read from the fuse block. The processor is configured with core voltage and system bus frequency based on the values read from the fuse block. The platform then performs its boot-up sequence.

    摘要翻译： 在处理器制造过程中，动态处理器配置和上电将处理器的熔丝块与配置信号进行编程。 处理器配置信号包括核心电压标识符和系统总线频率标识符。 当对平台施加电力时，使用控制信号来防止平台处理器相关电路的上电。 当平台等待完全上电时，保险丝盒通电。 当保险丝盒通电时，控制信号用于允许从保险丝盒读取配置信号。 基于从保险丝盒读取的值，处理器配置有核心电压和系统总线频率。 然后平台执行其启动顺序。

    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
    48.
    发明授权
    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock 有权
    将具有与系统时钟的可选择的相位差的I / O缓冲器与与系统时钟同步的远程I / O缓冲器进行时钟

    公开(公告)号：US06748549B1

    公开(公告)日：2004-06-08

    申请号：US09604049

    申请日：2000-06-26

    申请人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    发明人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    IPC分类号： G06F104

    CPC分类号： G01R31/31937

    摘要： Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.

    摘要翻译： 输入/输出（I / O）时钟相位调整电路，用于集成电路芯片的I / O缓冲电路。 在一个实施例中，集成电路芯片包括耦合以接收系统时钟的相位调整电路。 相位调整电路产生I / O时钟，I / O时钟由系统中用于I / O数据传输的集成电路芯片的I / O缓冲电路接收。 相位调整电路包括锁相环（PLL）电路，其被耦合以通过第一延迟电路接收系统时钟。 由PLL电路产生的I / O时钟通过PLL电路的反馈时钟输入端的第二延迟电路接收。 第一和第二延迟电路用于控制PLL电路相对于系统时钟产生的I / O时钟的相位。 在一个实施例中，第三延迟电路包括在集成电路的I / O缓冲电路的I / O数据路径中。 第三延迟电路使得来自集成电路的输入和输出数据传输被实时地与由相位调整电路产生的I / O时钟异相。

    Input circuit with non-delayed time blanking
    50.
    发明授权
    Input circuit with non-delayed time blanking 失效

    公开(公告)号：US06552570B2

    公开(公告)日：2003-04-22

    申请号：US09894187

    申请日：2001-06-27

    申请人： Gregory F. Taylor ,  Chi-Yeu Chao

    发明人： Gregory F. Taylor ,  Chi-Yeu Chao

    IPC分类号： H03K3356

    CPC分类号： H03K5/1252

    摘要： An input circuit that receives an input signal and generates an output signal as a function of the input signal includes a latching circuit and a time blanking circuit. The latching circuit detects a transition of the input signal and causes a corresponding transition of the output signal. The time blanking circuit prevents the output signal from transitioning again for a predetermined period. This period begins with essentially no delay from the transition of the output signal, which can reduce the input circuit's sensitivity to high frequency noise that may be present on transitions of the input signal.