利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

121 条记录 (耗时 0.014 秒)

    RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
    42.
    发明申请
    RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 失效
    半导体存储器接收器电路

    公开(公告)号：US20090059703A1

    公开(公告)日：2009-03-05

    申请号：US12172108

    申请日：2008-07-11

    申请人： Tae Jin Hwang ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Tae Jin Hwang ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222

    摘要： A receiver circuit is described herein, comprising a first data determining unit configured to detect and amplify a voltage level difference between first and second external data and generate first and second sense signals and to generate first internal data in response to the first and second sense signals, a first offset control unit configured to generate first and second offset signals in response to the first and second sense signals, the first and second offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a first code, a second data determining unit configured to detect and amplify the voltage level difference between the first and second external data to generate third and fourth sense signals and to generate second internal data in response to the third and fourth sense signals; and a second offset control unit for generating third and fourth offset signals in response to the third and fourth sense signals, the third and fourth offset signals swinging between a maximum voltage level and a minimum voltage level determined based on a second code, wherein the first data determining unit is configured to determine setup time and hold time of the first internal data in response to the third and fourth offset signals, and wherein the second data determining unit is configured to determine setup time and hold time of the second internal data in response to the first and second offset signals.

    摘要翻译： 本文描述了一种接收器电路，包括：第一数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，并产生第一和第二感测信号，并响应于第一和第二感测信号产生第一内部数据 第一偏移控制单元，被配置为响应于第一和第二感测信号产生第一和第二偏移信号，第一和第二偏移信号在基于第一代码确定的最大电压电平和最小电压电平之间摆动，第二偏移控制单元 数据确定单元，被配置为检测和放大第一和第二外部数据之间的电压电平差，以产生第三和第四感测信号，并响应于第三和第四感测信号产生第二内部数据; 以及第二偏移控制单元，用于响应于第三和第四感测信号产生第三和第四偏移信号，第三和第四偏移信号在基于第二代码确定的最大电压电平和最小电压电平之间摆动，其中第一和第二偏移信号 数据确定单元被配置为响应于第三和第四偏移信号来确定第一内部数据的建立时间和保持时间，并且其中第二数据确定单元被配置为响应于确定第二内部数据的建立时间和保持时间 到第一和第二偏移信号。

    Semiconductor apparatus
    45.
    发明授权
    Semiconductor apparatus 失效
    半导体装置

    公开(公告)号：US08171189B2

    公开(公告)日：2012-05-01

    申请号：US12648524

    申请日：2009-12-29

    申请人： Ji Wang Lee ,  Hee Woong Song ,  Tae Jin Hwang

    发明人： Ji Wang Lee ,  Hee Woong Song ,  Tae Jin Hwang

    IPC分类号： G06F3/00 ,  G06F5/00

    CPC分类号： G06F13/4072

    摘要： A semiconductor apparatus includes a clock input buffer, an asynchronous data input buffer, and a synchronous data input buffer. The clock input buffer is configured to buffer an external clocks in order to generate an internal clock. The asynchronous data input buffer is configured to buffer data input through a data pad and output the buffered data. The synchronous data input buffer is configured to be synchronous with the internal clock to buffer the buffered data. The semiconductor apparatus is arranged so that the length of a line for transferring the internal clock to the synchronous data input buffer and the length of a line for transferring the buffered data to the synchronous data input buffer are substantially equal to each other.

    摘要翻译： 半导体装置包括时钟输入缓冲器，异步数据输入缓冲器和同步数据输入缓冲器。 时钟输入缓冲器配置为缓冲外部时钟以产生内部时钟。 异步数据输入缓冲器被配置为缓冲通过数据焊盘输入的数据并输出缓冲的数据。 同步数据输入缓冲器被配置为与内部时钟同步以缓冲缓冲的数据。 半导体装置被布置成使得用于将内部时钟传送到同步数据输入缓冲器的线的长度和用于将缓冲数据传送到同步数据输入缓冲器的线的长度基本上彼此相等。

    Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same
    48.
    发明授权
    Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same 失效
    半导体存储装置的电压电平比较电路，使用电压电平比较电路的电压调整电路和使用其的半导体存储装置

    公开(公告)号：US08023356B2

    公开(公告)日：2011-09-20

    申请号：US12336423

    申请日：2008-12-16

    申请人： Ic-Su Oh ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    发明人： Ic-Su Oh ,  Yong-Ju Kim ,  Sung-Woo Han ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee ,  Jae-Min Jang ,  Chang-Kun Park

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the external voltage as the output voltage.

    摘要翻译： 半导体存储装置的电压调整电路包括：控制电压生成部，其被配置为响应于控制信号分配用于选择性地输出多个分配电压的外部电压作为控制电压，所述多个分配电压各自具有不同的电压 电平，比较单元，被配置为包括电压供应单元，其被配置为响应于所述电平的电平而控制提供给第一节点的外部电压和第二节点，如果输出电压的电平高于参考电压的电平 以及检测信号生成单元，被配置为根据输出电压和参考电压的电平来降低第一和第二节点的电位电平，并输出第二节点的电位电平作为检测信号，以及 电压产生单元，被配置为根据检测信号的电位来驱动外部电压 并输出外部电压作为输出电压。

    Delay locked loop circuit of semiconductor device
    50.
    发明授权
    Delay locked loop circuit of semiconductor device 有权
    半导体器件的延迟锁定环路

    公开(公告)号：US07990785B2

    公开(公告)日：2011-08-02

    申请号：US12262517

    申请日：2008-10-31

    申请人： Hee-Woong Song ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Hee-Woong Song ,  Kun-Woo Park ,  Yong-Ju Kim ,  Ic-Su Oh ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： G11C7/00

    CPC分类号： G11C29/02 ,  G11C7/22 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/0812 ,  H03L7/089 ,  H03L7/095

    摘要： A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals.

    摘要翻译： 半导体存储器件包括可以根据高频系统时钟控制数据的输入/输出定时的延迟锁定环电路。 半导体存储装置包括：相位比较器，被配置为检测内部时钟和参考时钟之间的相位差，以输出具有与检测到的相位差相对应的脉冲宽度的状态信号;相位调整器，被配置为生成用于确定 对应于用于锁定内部时钟的相位的状态信号的延迟时间，配置成将数字代码转换为模拟电压的数模转换器，以及被配置为根据偏置来延迟内部时钟的多相延迟信号发生器 对应于模拟电压的电压反馈延迟的内部时钟作为内部时钟，并产生多相延迟信号。