公开(公告)号：US08324061B2

公开(公告)日：2012-12-04

申请号：US13129419

申请日：2011-02-17

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Gaobo Xu ,  Lingkuan Meng ,  Tao Yang ,  Dapeng Chen

IPC: H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/76819 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一栅极叠层，第一栅叠层在第一栅极导体和半导体衬底之间包括第一栅极导体和第一栅极电介质; 在半导体衬底上形成源/漏区; 在所述半导体衬底和所述第一栅极叠层上形成包括至少一个牺牲层和所述牺牲层下方的至少一个绝缘层的多层结构; 在所述多层结构上执行第一RIE; 在所述多层结构上执行第二RIE; 相对于绝缘层选择性地蚀刻第一栅极叠层，其中去除第一栅极导体并在绝缘层中形成开口; 以及在所述开口中形成第二栅极导体。

公开(公告)号：US20120139054A1

公开(公告)日：2012-06-07

申请号：US13108742

申请日：2011-05-16

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7845

Abstract: The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a channel formed on the semiconductor substrate (202, 302); a gate dielectric layer (204, 304) formed on the channel; a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and a source and a drain formed on both sides of the gate; wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Abstract translation: 本发明涉及具有可调节通道应力的装置及其方法。 提供一种包括半导体衬底（202,302）的MOS器件（200,300）。 形成在半导体衬底（202,302）上的沟道; 形成在所述沟道上的栅介质层（204,304）; 形成在栅极介电层（204,304）上的栅极导体（206,306）; 以及形成在闸门两侧的源极和漏极; 其中所述栅极导体（206,306）具有用于产生要施加到所述沟道的第一应力的形状，以便调整所述沟道中的载流子的迁移率。 在本发明中，可以通过控制蚀刻工艺参数来调整栅极导体的形状，从而可以方便地调节通道中的应力，同时可以与产生应力的其他机构组合使用以获得期望的 通道压力。

公开(公告)号：US08022408B2

公开(公告)日：2011-09-20

申请号：US12659776

申请日：2010-03-22

Applicant: Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

Inventor： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

IPC: H01L29/04

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/90 ,  Y10S977/932 ,  Y10S977/943

Abstract: Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

Abstract translation: 示例性实施例涉及具有其中可以在基板上形成具有相对较细的线宽的结晶纳米线膜的结构的晶体纳米线基板及其制造方法，以及使用其制造薄膜晶体管的方法 。 制造结晶纳米线基板的方法可以包括制备基板，在基板上形成绝缘膜，在绝缘膜上形成硅膜，将绝缘膜和硅膜图案化成带状，减小线宽 绝缘膜通过底切蚀刻绝缘膜的至少一个侧面，并且通过使硅膜熔化和结晶而在绝缘膜的上表面上形成自对准硅纳米线膜。

公开(公告)号：US20110089998A1

公开(公告)日：2011-04-21

申请号：US12926475

申请日：2010-11-19

Applicant: Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

Inventor： Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

IPC: G05F3/02

CPC classification number: H03K19/01714

Abstract: An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor.

公开(公告)号：US20100208368A1

公开(公告)日：2010-08-19

申请号：US12662607

申请日：2010-04-26

Applicant: Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

Inventor： Huaxiang Yin ,  Hyuck Lim ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

IPC: G02B7/02

CPC classification number: H01L27/14627 ,  H01L27/14621 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02327

Abstract: A microlens, an image sensor including the microlens, a method of forming the microlens and a method of manufacturing the image sensor are provided. The microlens includes a polysilicon pattern, having a cylindrical shape, formed on a substrate, and a round-type shell portion enclosing the polysilicon pattern. The microlens may further include a filler material filling an interior of the shell portion, or a second shell portion covering the first shell portion. The method of forming a microlens includes forming a silicon pattern on a semiconductor substrate having a lower structure, forming a capping film on the semiconductor substrate over the silicon pattern, annealing the silicon pattern and the capping film altering the silicon pattern to a polysilicon pattern having a cylindrical shape and the capping film to a shell portion for a round-type microlens, and filling an interior of the shell portion with a lens material through an opening between the semiconductor substrate and an edge of the shell portion. The image sensor includes a microlens formed by a similar method and a photodiode having a cylindrical shape.

Abstract translation: 提供微透镜，包括微透镜的图像传感器，形成微透镜的方法和制造图像传感器的方法。 微透镜包括形成在基板上的具有圆柱形状的多晶硅图案和包围多晶硅图案的圆形外壳部分。 微透镜还可以包括填充壳体部分的内部的填充材料或覆盖第一壳体部分的第二壳体部分。 形成微透镜的方法包括在具有较低结构的半导体衬底上形成硅图案，在硅图案上的半导体衬底上形成覆盖膜，使硅图案和覆盖膜退火，将硅图案改变为具有 圆筒形，并且封盖膜用于圆形微透镜的外壳部分，并且通过半导体基板和外壳部分的边缘之间的开口用透镜材料填充外壳部分的内部。 图像传感器包括通过类似方法形成的微透镜和具有圆柱形状的光电二极管。

公开(公告)号：US07723168B2

公开(公告)日：2010-05-25

申请号：US11283874

申请日：2005-11-22

Applicant: Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

Inventor： Huaxiang Yin ,  Takashi Noguchi ,  Wenxu Xianyu ,  Kyung-bae Park

IPC: H01L21/00

CPC classification number: H01L21/02675 ,  H01L21/2026 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/12 ,  H01L27/1281

Abstract: A method of manufacturing a polycrystalline Si film and a method of manufacturing a stacked transistor are provided. The method of manufacturing the polycrystalline Si film includes preparing an insulating substrate on which is formed a transistor that includes a poly-Si active layer, a gate insulating layer, and a gate, sequentially formed, forming an interconnection metal line separated from the gate, forming an insulating layer that covers the transistor and the interconnection metal line, forming an amorphous silicon layer on the insulating layer; and annealing the amorphous silicon layer.

Abstract translation: 提供一种制造多晶Si膜的方法和制造堆叠晶体管的方法。 制造多晶Si膜的方法包括制备绝缘基板，其上形成有依次形成的多晶硅，具有多晶硅有源层，栅极绝缘层和栅极，形成与栅极分离的互连金属线， 形成覆盖晶体管和互连金属线的绝缘层，在绝缘层上形成非晶硅层; 并退火非晶硅层。

公开(公告)号：US20100059744A1

公开(公告)日：2010-03-11

申请号：US12453106

申请日：2009-04-29

Applicant: Huaxiang YIN ,  Ihun SONG ,  Sunil KIM ,  Youngsoo PARK

Inventor： Huaxiang YIN ,  Ihun SONG ,  Sunil KIM ,  Youngsoo PARK

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L27/1225 ,  H01L27/1237 ,  H01L29/66833 ,  H01L29/792

Abstract: A transistor, an inverter including the transistor, and methods of manufacturing the inverter and the transistor. A gate insulating layer of the transistor has a charge trap region. A threshold voltage may be moved in a positive (+) direction by trapping charges in the charge trap region. The transistor may be an enhancement mode oxide thin-film transistor (TFT) and may be used as an element of the inverter.

Abstract translation: 晶体管，包括晶体管的反相器，以及制造反相器和晶体管的方法。 晶体管的栅极绝缘层具有电荷陷阱区域。 通过在电荷陷阱区域中捕获电荷，可以在正（+）方向上移动阈值电压。 晶体管可以是增强型氧化物薄膜晶体管（TFT），并且可以用作逆变器的元件。

公开(公告)号：US20100041214A1

公开(公告)日：2010-02-18

申请号：US12461315

申请日：2009-08-07

Applicant: Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Xiaoxin Zhang ,  Huaxiang Yin

Inventor： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Xiaoxin Zhang ,  Huaxiang Yin

IPC: H01L21/20

CPC classification number: H01L21/02636 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02686

Abstract: A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or germanium seed layer on the portion of the substrate exposed through the window; depositing a silicon or germanium material layer, which are crystallization target material layers, on the epitaxial growth silicon 6r germanium seed layer and the insulator; and crystallizing the crystallization target material layer by melting and cooling the crystallization target material layer.

Abstract translation: 提供了高质量的单晶基板及其制造方法。 制造单晶衬底的方法包括：在衬底上形成绝缘体; 在所述绝缘体中形成窗口，所述窗口暴露所述基板的一部分; 在通过窗户暴露的衬底的部分上形成外延生长硅或锗种子层; 在外延生长硅6r锗种子层和绝缘体上沉积作为结晶靶材料层的硅或锗材料层; 并且通过熔化和冷却结晶化目标材料层来使结晶目标材料层结晶。

公开(公告)号：US20090162981A1

公开(公告)日：2009-06-25

申请号：US12372541

申请日：2009-02-17

Applicant: Huaxiang YIN ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

Inventor： Huaxiang YIN ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-young Kim

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/7855

Abstract: A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a substrate; a buffer layer formed on the substrate; a source and a drain spaced apart from each other on the buffer layer; a channel layer formed on the buffer layer to connect the source and the drain with each other; and a gate formed on the buffer layer to be spaced apart from the source, the drain and the channel layer.

Abstract translation: 提供薄膜晶体管及其制造方法。 薄膜晶体管包括基板; 形成在所述基板上的缓冲层; 在缓冲层上彼此间隔开的源极和漏极; 形成在所述缓冲层上的沟道层，以将所述源极和所述漏极彼此连接; 以及形成在缓冲层上以与源极，漏极和沟道层间隔开的栅极。

公开(公告)号：US07470579B2

公开(公告)日：2008-12-30

申请号：US11557360

申请日：2006-11-07

Applicant: Hyuk Lim ,  Takashi Noguchi ,  Jong-man Kim ,  Kyung-bae Park ,  Huaxiang Yin

Inventor： Hyuk Lim ,  Takashi Noguchi ,  Jong-man Kim ,  Kyung-bae Park ,  Huaxiang Yin

IPC: H01L21/336

CPC classification number: H01L29/78621 ,  H01L29/66757

Abstract: A thin film transistor having an offset or a lightly doped drain (LDD) structure by self alignment and a method of fabricating the same comprises a substrate, a silicon layer disposed on the substrate and including a channel region, a source region and a drain region at both sides of the channel region, and offset regions, each offset regions disposed between the channel region and one of the source and drain regions at both sides of the channel region, a gate insulating layer covering the channel region and the offset regions disposed at both sides of the channel region excluding the source and drain regions, and a gate layer formed on the channel region excluding the offset regions. The thin film transistor has the structure in which an offset or LDD is obtained without an additional mask process.

Abstract translation: 具有通过自对准的偏移或轻掺杂漏极（LDD）结构的薄膜晶体管及其制造方法包括：衬底，设置在衬底上的硅层，并且包括沟道区，源极区和漏极区 在通道区域的两侧和偏移区域，每个偏移区域设置在沟道区域和沟道区域两侧的源极和漏极区域之一之间，覆盖沟道区域的栅极绝缘层和设置在沟道区域的偏移区域 除了源极和漏极区域之外的沟道区域的两侧，以及形成在除偏移区域之外的沟道区域上的栅极层。 薄膜晶体管具有在没有附加掩模处理的情况下获得偏移或LDD的结构。