公开(公告)号：US20080135876A1

公开(公告)日：2008-06-12

申请号：US12033065

申请日：2008-02-19

Applicant: Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

Inventor： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

IPC: H01L29/94

CPC classification number: H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.

Abstract translation: 提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。 制造沟槽电容器的一些方法包括在衬底上形成第一层。 在与衬底相对的第一层上形成第二层。 形成在第一和第二层的顶部上具有开口的掩模。 通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。 除去第二层下面的第一层的一部分，以在第二层下形成底切区域。 在第二层下方的底切区域中形成绝缘层套环。 形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。 掩埋板沿着第二沟槽形成在衬底中。 介电层形成在第二沟槽的内壁和底部上。 在电介质层上的第二沟槽中形成存储电极。

公开(公告)号：US07354821B2

公开(公告)日：2008-04-08

申请号：US11037626

申请日：2005-01-18

Applicant: Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

Inventor： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

IPC: H01L21/8242 ,  H01L21/336

CPC classification number: H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.

Abstract translation: 提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。 制造沟槽电容器的一些方法包括在衬底上形成第一层。 在与衬底相对的第一层上形成第二层。 形成在第一和第二层的顶部上具有开口的掩模。 通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。 除去第二层下面的第一层的一部分，以在第二层下形成底切区域。 在第二层下方的底切区域中形成绝缘层套环。 形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。 掩埋板沿着第二沟槽形成在衬底中。 介电层形成在第二沟槽的内壁和底部上。 在电介质层上的第二沟槽中形成存储电极。

公开(公告)号：US20070127611A1

公开(公告)日：2007-06-07

申请号：US11521739

申请日：2006-09-15

Applicant: Young-Jun Chong ,  Min-Soo Kang ,  Sung-Jin You ,  Tae-Jin Chung

Inventor： Young-Jun Chong ,  Min-Soo Kang ,  Sung-Jin You ,  Tae-Jin Chung

IPC: H04L7/00 ,  H04L27/22

CPC classification number: H04L27/0014 ,  H04B1/30 ,  H04L2027/003 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: A non-coherent synchronous direct-conversion receiving apparatus is provided. The apparatus includes a RF receiving unit, an I/Q ADC unit, and a digital signal processing unit for analyzing the digital signal received from the I/Q ADC unit to adjust a bandwidth of a variable receiving filtering unit according to the analyzing result, compensating a frequency offset to be correspondent with a symbol transmitting rate by extracting frequency offset information from the digital signal, compensating a frequency offset using the analyzing result, and applying a voltage corresponding to a sum of compensating values to the RF receiving unit. Therefore, the apparatus can compensate a frequency offset regardless of the magnitude of a frequency offset and performs a stable AFC operation through varying the bandwidth of a receiving filter by estimating the frequency offset with only data information, and adjusting a reference frequency twice through an interface signal.

Abstract translation: 提供了非相干同步直接转换接收装置。 该装置包括RF接收单元，I / Q ADC单元和数字信号处理单元，用于分析从I / Q ADC单元接收的数字信号，以根据分析结果调整可变接收滤波单元的带宽， 通过从数字信号中提取频率偏移信息来补偿与符号发送速率相对应的频率偏移，使用分析结果补偿频率偏移，以及将对应于补偿值的和的电压施加到RF接收单元。 因此，无论频偏的大小如何，该装置可以补偿频率偏移，并且通过仅利用数据信息估计频偏，并通过接口调整参考频率两次来改变接收滤波器的带宽来执行稳定的AFC操作 信号。

公开(公告)号：US20070099419A1

公开(公告)日：2007-05-03

申请号：US11641138

申请日：2006-12-19

Applicant: Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

Inventor： Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

IPC: H01L21/44

CPC classification number: H01L28/65 ,  H01L28/40

Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

公开(公告)号：US20070058600A1

公开(公告)日：2007-03-15

申请号：US11493561

申请日：2006-07-27

Applicant: Soo-Jin Chung ,  Kill-Yeon Kim

Inventor： Soo-Jin Chung ,  Kill-Yeon Kim

IPC: H04Q7/24

CPC classification number: H04L47/32 ,  H04L47/10 ,  H04L47/14 ,  H04L47/266 ,  H04L47/30 ,  H04L49/90 ,  H04W28/12 ,  H04W72/1252 ,  H04W84/12 ,  H04W88/08

Abstract: Packet flow control in a Wireless Local Area Network (WLAN) system includes controlling packet flow of the WLAN using a pause frame depending on whether a buffer of an (Access Point) AP is saturated, thereby preventing packet loss and channel dissipation and improving the efficiency with which resources of the WLAN are utilized.

Abstract translation: 无线局域网（WLAN）系统中的分组流控制包括根据（接入点）AP的缓冲器是否饱和来控制WLAN的分组流量，从而防止分组丢失和信道耗散并提高效率 利用WLAN的资源。

公开(公告)号：US20070054477A1

公开(公告)日：2007-03-08

申请号：US11506723

申请日：2006-08-18

Applicant: Dong-byum Kim ,  Se-jin Chung

Inventor： Dong-byum Kim ,  Se-jin Chung

IPC: H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1285 ,  H01L29/045

Abstract: Provided are a method of forming a polycrystalline silicon thin film with improved electrical characteristics and a method of manufacturing a thin film transistor using the method of forming the polycrystalline silicon thin film. The method includes forming an amorphous silicon thin film on a substrate, partially melting a portion of the amorphous silicon thin film by irradiating the portion of the amorphous silicon thin film with a laser beam having a low energy density, forming polycrystalline silicon grains with a predetermined crystalline arrangement by crystallizing the partially molten portion of the amorphous silicon thin film, completely melting a portion of the polycrystalline silicon grains and a portion of the amorphous silicon thin film by irradiation of a laser beam having a high energy density while repeatedly moving the substrate by a predetermined distance, and growing the polycrystalline silicon grains by crystallizing the completely molten silicon homogeneously with the predetermined crystalline arrangement.

Abstract translation: 提供一种形成具有改善的电特性的多晶硅薄膜的方法和使用形成多晶硅薄膜的方法制造薄膜晶体管的方法。 该方法包括在衬底上形成非晶硅薄膜，通过用具有低能量密度的激光束照射非晶硅薄膜的一部分来部分地熔化非晶硅薄膜的一部分，形成具有预定的多晶硅晶粒的多晶硅晶粒 通过使非晶硅薄膜的部分熔融部分结晶，通过照射具有高能量密度的激光束将多晶硅晶粒的一部分和非晶硅薄膜的一部分完全熔化，同时通过 预定距离，并且通过使预定结晶布置均匀地结晶完全熔融的硅而生长多晶硅晶粒。

公开(公告)号：US20070052713A1

公开(公告)日：2007-03-08

申请号：US11415721

申请日：2006-05-02

Applicant: Young-Jin Chung ,  Kil-Whan Lee

Inventor： Young-Jin Chung ,  Kil-Whan Lee

IPC: G06T1/00

CPC classification number: G06T15/04

Abstract: In systems and methods for graphic reproduction of an image including textural information, multiple rows or blocks of texture data can be retrieved from system memory in response to the single read command. In this manner, efficient use of system bus is achieved, and an increase in the texture cache hit ratio is realized, leading to more efficient system operation, and reduced system bus usage for texture data retrieval.

Abstract translation: 在用于图形再现包括纹理信息的图像的系统和方法中，响应于单个读取命令，可以从系统存储器检索纹理数据的多个行或块。 以这种方式，实现了系统总线的有效使用，并且实现了纹理缓存命中率的增加，导致更有效的系统操作，并减少了纹理数据检索的系统总线使用。

公开(公告)号：US07172946B2

公开(公告)日：2007-02-06

申请号：US10629430

申请日：2003-07-29

Applicant: Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

Inventor： Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

IPC: H01L21/20

CPC classification number: H01L28/65 ,  H01L28/40

Abstract: Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

Abstract translation: 用于制造半导体存储器件的方法可以包括在半导体衬底上形成用于第一电极的第一导电层，在第一导电层上形成电介质层，以及在电介质层上形成用于第二电极的第二导电层。 可以去除第二导电层和电介质层的部分，并且可以在第二导电层和电介质层上进行热处理。 热处理可以减少第二导电层和电介质层之间的界面应力和/或固化电介质层。 此外，在热处理期间和之后，电介质层可以保持在非晶状态。

公开(公告)号：US20060274077A1

公开(公告)日：2006-12-07

申请号：US11365600

申请日：2006-03-02

Applicant: Young-Jin Chung ,  Kil-Whan Lee ,  Mahn-Gee Park

Inventor： Young-Jin Chung ,  Kil-Whan Lee ,  Mahn-Gee Park

IPC: G09G5/00

CPC classification number: G06T1/60 ,  G06T15/005

Abstract: An apparatus according to an example embodiment of the present invention, may process data of a present span. During processing, data corresponding to an address of the start data of the next span may be prefetched from the external memory device based on information related to the presently processed data. The prefetched data may store in the cache memory.

公开(公告)号：US20060262052A1

公开(公告)日：2006-11-23

申请号：US11434820

申请日：2006-05-17

Applicant: Chang Kim ,  Ho Lee ,  Jin Chung ,  Sun Kang ,  Do Kim ,  Hong Kim

Inventor： Chang Kim ,  Ho Lee ,  Jin Chung ,  Sun Kang ,  Do Kim ,  Hong Kim

IPC: G09G3/30

CPC classification number: H01L51/5228 ,  H01L27/3246 ,  H01L27/3258 ,  H01L51/5218 ,  H01L51/5234 ,  H01L2251/5315 ,  H01L2251/558

Abstract: An organic electroluminescent device, adapted to enhance device reliability while allowing simplification of a manufacturing process, and a method for manufacturing the same are disclosed. The organic electroluminescent (EL) device, comprising a substrate, TFTs located in respective unit pixel regions on the substrate, a first insulation layer to insulate the TFTs, first electrodes formed on the first insulation layer while contacting the TFTs, respectively, a partition wall positioned between the unit pixel regions on the first insulation layer, a subsidiary electrode formed on the partition wall, an organic light emitting layer positioned on the first electrodes, an insulation part to insulate each first electrode from an associated subsidiary electrode, and a second electrode positioned on the organic light emitting layer and connected with the subsidiary electrode.