公开(公告)号：US20050212026A1

公开(公告)日：2005-09-29

申请号：US11037626

申请日：2005-01-18

申请人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

发明人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

IPC分类号： H01L27/108 ,  H01L21/334 ,  H01L21/82 ,  H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.

摘要翻译： 提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。 制造沟槽电容器的一些方法包括在衬底上形成第一层。 在与衬底相对的第一层上形成第二层。 形成在第一和第二层的顶部上具有开口的掩模。 通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。 除去第二层下面的第一层的一部分，以在第二层下形成底切区域。 在第二层下方的底切区域中形成绝缘层套环。 形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。 掩埋板沿着第二沟槽形成在衬底中。 介电层形成在第二沟槽的内壁和底部上。 在电介质层上的第二沟槽中形成存储电极。

公开(公告)号：US07531861B2

公开(公告)日：2009-05-12

申请号：US12033065

申请日：2008-02-19

申请人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

发明人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

IPC分类号： H01L29/94

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.

摘要翻译： 提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。 制造沟槽电容器的一些方法包括在衬底上形成第一层。 在与衬底相对的第一层上形成第二层。 形成在第一和第二层的顶部上具有开口的掩模。 通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。 除去第二层下面的第一层的一部分，以在第二层下形成底切区域。 在第二层下方的底切区域中形成绝缘层套环。 形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。 掩埋板沿着第二沟槽形成在衬底中。 介电层形成在第二沟槽的内壁和底部上。 在电介质层上的第二沟槽中形成存储电极。

公开(公告)号：US20080135876A1

公开(公告)日：2008-06-12

申请号：US12033065

申请日：2008-02-19

申请人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

发明人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

IPC分类号： H01L29/94

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.

摘要翻译： 提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。 制造沟槽电容器的一些方法包括在衬底上形成第一层。 在与衬底相对的第一层上形成第二层。 形成在第一和第二层的顶部上具有开口的掩模。 通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。 除去第二层下面的第一层的一部分，以在第二层下形成底切区域。 在第二层下方的底切区域中形成绝缘层套环。 形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。 掩埋板沿着第二沟槽形成在衬底中。 介电层形成在第二沟槽的内壁和底部上。 在电介质层上的第二沟槽中形成存储电极。

公开(公告)号：US07354821B2

公开(公告)日：2008-04-08

申请号：US11037626

申请日：2005-01-18

申请人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

发明人： Suk-jin Chung ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim ,  Jae-soon Lim ,  Young-geun Park

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L27/1087 ,  H01L29/66181 ,  H01L29/945

摘要： Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench. A storage electrode is formed in the second trench on the dielectric layer.

摘要翻译： 提供了在底切区域中具有绝缘层套环的沟槽电容器和制造这种沟槽电容器的方法。 制造沟槽电容器的一些方法包括在衬底上形成第一层。 在与衬底相对的第一层上形成第二层。 形成在第一和第二层的顶部上具有开口的掩模。 通过从掩模中的开口去除第一层和第二层的一部分来形成第一沟槽。 除去第二层下面的第一层的一部分，以在第二层下形成底切区域。 在第二层下方的底切区域中形成绝缘层套环。 形成第二沟槽，其通过从掩模中的开口去除衬底的一部分而从第一沟槽延伸。 掩埋板沿着第二沟槽形成在衬底中。 介电层形成在第二沟槽的内壁和底部上。 在电介质层上的第二沟槽中形成存储电极。

公开(公告)号：US20110095397A1

公开(公告)日：2011-04-28

申请号：US12909289

申请日：2010-10-21

申请人： Suk-jin Chung ,  Jae-hyoung Choi ,  Youn-soo Kim ,  Jae-soon Lim ,  Sang-yeol Kang

发明人： Suk-jin Chung ,  Jae-hyoung Choi ,  Youn-soo Kim ,  Jae-soon Lim ,  Sang-yeol Kang

IPC分类号： H01L29/92 ,  H01G4/30

CPC分类号： H01L27/10852 ,  H01L21/02175 ,  H01L21/02183 ,  H01L21/02304 ,  H01L21/02362 ,  H01L28/40

摘要： Semiconductor structures including a first conductive layer; a dielectric layer on the first conductive layer; a second conductive layer on the dielectric layer; and a crystallized seed layer in at least one of a first portion between the first conductive layer and the dielectric layer and a second portion between the dielectric layer and the second conductive layer. Related capacitors and methods are also provided herein.

摘要翻译： 包括第一导电层的半导体结构; 第一导电层上的电介质层; 介电层上的第二导电层; 以及在所述第一导电层和所述电介质层之间的第一部分中的至少一个中的结晶晶种层和所述介电层和所述第二导电层之间的第二部分。 本文还提供了相关的电容器和方法。

公开(公告)号：US20060148193A1

公开(公告)日：2006-07-06

申请号：US11374349

申请日：2006-03-13

申请人： Kwang-hee Lee ,  Cha-young Yoo ,  Han-Jin Lim ,  Sung-tae Kim ,  Suk-jin Chung ,  Wan-don Kim ,  Jung-hee Chung ,  Jin-il Lee

发明人： Kwang-hee Lee ,  Cha-young Yoo ,  Han-Jin Lim ,  Sung-tae Kim ,  Suk-jin Chung ,  Wan-don Kim ,  Jung-hee Chung ,  Jin-il Lee

IPC分类号： H01L21/44

CPC分类号： C23C16/18 ,  H01L21/28556 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2-1 ccm and oxygen at a flow rate of 20-60 sccm, and depositing the ruthenium film at a temperature of 330-430° C. under a pressure of 0.5-5 Torr using chemical vapor deposition (CVD).

摘要翻译： 提供1）一种在单一工艺条件下形成钌膜的方法，由此保持钌膜对下层的高附着性，以及2）使用这种方法制造金属 - 绝缘体 - 金属（MIM）电容器的方法 钌膜成型方法。 形成钌膜的方法包括以0.2-1ccm的流速和20-60sccm的流量的氧供给双（异庚烷-2,4-二酮）降冰片二烯钌，并将钌膜以 在0.5-5乇的压力下使用化学气相沉积（CVD）来制备330-430℃。

公开(公告)号：US07049232B2

公开(公告)日：2006-05-23

申请号：US10657596

申请日：2003-09-08

申请人： Kwang-hee Lee ,  Cha-young Yoo ,  Han-jin Lim ,  Sung-tae Kim ,  Suk-jin Chung ,  Wan-don Kim ,  Jung-hee Chung ,  Jin-il Lee

发明人： Kwang-hee Lee ,  Cha-young Yoo ,  Han-jin Lim ,  Sung-tae Kim ,  Suk-jin Chung ,  Wan-don Kim ,  Jung-hee Chung ,  Jin-il Lee

IPC分类号： H01L21/44

CPC分类号： C23C16/18 ,  H01L21/28556 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2–1 ccm and oxygen at a flow rate of 20–60 sccm, and depositing the ruthenium film at a temperature of 330–430° C. under a pressure of 0.5–5 Torr using chemical vapor deposition (CVD).

公开(公告)号：US09076647B2

公开(公告)日：2015-07-07

申请号：US13459136

申请日：2012-04-28

申请人： Suk-jin Chung ,  Youn-soo Kim ,  Cha-young Yoo ,  Jong-cheol Lee ,  Sang-yeol Kang

发明人： Suk-jin Chung ,  Youn-soo Kim ,  Cha-young Yoo ,  Jong-cheol Lee ,  Sang-yeol Kang

IPC分类号： H01L21/31 ,  H01L21/02 ,  H01L27/108 ,  H01L27/115 ,  H01L49/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

CPC分类号： H01L21/02178 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/28282 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/91 ,  H01L29/66795 ,  H01L29/7926

摘要： A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.

摘要翻译： 一种形成氧化物层的方法。 该方法包括：在基板的表面上形成反应抑制性官能团层; 在反应抑制官能团的层上形成金属或半导体的前体层; 以及氧化金属或半导体的前体以获得金属氧化物或半导体氧化物的层。 根据该方法，可以形成具有高厚度均匀性的氧化物层，并且可以制造具有优异电特性的半导体器件。

公开(公告)号：US07335550B2

公开(公告)日：2008-02-26

申请号：US11641138

申请日：2006-12-19

申请人： Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

发明人： Jae-hyoung Choi ,  Wan-don Kim ,  Cha-young Yoo ,  Suk-jin Chung

IPC分类号： H01L21/8234

CPC分类号： H01L28/65 ,  H01L28/40

摘要： Methods for fabricating semiconductor memory devices may include forming a first conductive layer for a first electrode on a semiconductor substrate, forming a dielectric layer on the first conductive layer, and forming a second conductive layer for a second electrode on the dielectric layer. Portions of the second conductive layer and the dielectric layer can be removed, and a thermal process can be performed on the second conductive layer and the dielectric layer. The thermal process can reduce interface stress between the second conductive layer and the dielectric layer and/or cure the dielectric layer. In addition, the dielectric layer may be maintained in an amorphous state during and after the thermal process.

摘要翻译： 用于制造半导体存储器件的方法可以包括在半导体衬底上形成用于第一电极的第一导电层，在第一导电层上形成电介质层，以及在电介质层上形成用于第二电极的第二导电层。 可以去除第二导电层和电介质层的部分，并且可以在第二导电层和电介质层上进行热处理。 热处理可以减少第二导电层和电介质层之间的界面应力和/或固化电介质层。 此外，在热处理期间和之后，电介质层可以保持在非晶状态。

公开(公告)号：US20120276721A1

公开(公告)日：2012-11-01

申请号：US13459136

申请日：2012-04-28

申请人： Suk-jin Chung ,  Jong-cheol Lee ,  Youn-soo Kim ,  Cha-young Yoo ,  Sang-yeol Kang

发明人： Suk-jin Chung ,  Jong-cheol Lee ,  Youn-soo Kim ,  Cha-young Yoo ,  Sang-yeol Kang

IPC分类号： H01L21/20

CPC分类号： H01L21/02178 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/28282 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/1157 ,  H01L27/11582 ,  H01L28/91 ,  H01L29/66795 ,  H01L29/7926

摘要： A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.

摘要翻译： 一种形成氧化物层的方法。 该方法包括：在基板的表面上形成反应抑制性官能团层; 在反应抑制官能团的层上形成金属或半导体的前体层; 以及氧化金属或半导体的前体以获得金属氧化物或半导体氧化物的层。 根据该方法，可以形成具有高厚度均匀性的氧化物层，并且可以制造具有优异电特性的半导体器件。