Abstract:
A phase-arrayed device includes: a signal processing circuit arranged to generate a specific signal; a first phase-arrayed channel arranged to provide a first phase-arrayed signal according to the specific signal; a first conducting path arranged to conduct the specific signal to the first phase-arrayed channel; a second conducting path arranged to conduct the first phase-arrayed signal to the signal processing circuit; and a detecting circuit, arranged to detect a mismatch between the first phase-arrayed signal and a reference signal to generate a detecting signal utilized for calibrating the first phase-arrayed signal.
Abstract:
The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.
Abstract:
A surrogate addition device is described that adds a surrogate compound at a uniform transport rate to a flowing sample stream. The surrogate addition device includes a surrogate reservoir, a flow chamber, and a diffusion barrier. The surrogate reservoir can be configured to contain a surrogate solution where the surrogate solution includes a surrogate compound. The flow chamber includes an inlet port and an outlet port. At least a portion of the diffusion barrier is disposed in between the surrogate reservoir and the flow chamber. The diffusion barrier may include an inner surface that forms a wall of the surrogate reservoir, and an outer surface that forms a wall of the flow chamber. The flow chamber can be configured to receive a flowing sample solution across the outer surface of the diffusion barrier and also to diffuse the surrogate compound from the surrogate reservoir to the flow chamber.
Abstract:
A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.
Abstract:
An electric air pump has a pumping assembly, an outer bracket and an inlet plate. The pumping assembly has a casing. The outer bracket is connected pivotally to the pumping assembly and has a faceplate mounted pivotally on an open top of the casing of the pumping assembly and selectively hermetically contacting a top annular edge of an open top of the casing. A locking hole is defined through the faceplate. The inlet plate is mounted securely in the casing, located between the casing and the outer bracket and has a resilient locking hook selectively hooking in the locking hole of the outer bracket. The electric air pump is capable of inflating and deflating an inflatable product without cooperating with external devices.
Abstract:
A semiconductor circuit is provided. The semiconductor circuit includes a metal layer, a conductive layer disposed under the metal layer and a semiconductor device disposed under the conductive layer. The metal layer forms an inductor device. The semiconductor device is coupled to the inductor device.
Abstract:
A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.
Abstract:
An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.
Abstract:
A load device has tunable capacitive units including at least a first tunable capacitive unit and a second tunable capacitive unit with different inherent capacitive characteristics, respectively. Each of the first tunable capacitive unit and the second tunable capacitive unit has a first node and a second node, where the first nodes of the first tunable capacitive unit and the second tunable capacitive unit are coupled to a first voltage, the second node of the first tunable capacitive unit is coupled to a second voltage, and the second node of the second tunable capacitive unit is coupled to a third voltage.
Abstract:
An embodiment of the voltage controlled oscillator is provided. The oscillator comprises a first inductor set, a second inductor set, a second capacitor, a voltage source and a negative resistance element. The inductance of the second inductor set is k times the inductance of the first inductor set. The voltage source applies an ac voltage to the second inductor set. The negative resistance element is coupled to the second inductor set to provide a negative resistance to resonate the second capacitor at the second inductor set.