利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

258 条记录 (耗时 0.032 秒)

    Viterbi decoder
    41.
    发明授权
    Viterbi decoder 失效
    维特比解码器

    公开(公告)号：US5881075A

    公开(公告)日：1999-03-09

    申请号：US814828

    申请日：1997-03-11

    申请人： Jun-jin Kong ,  Yong-woo Park

    发明人： Jun-jin Kong ,  Yong-woo Park

    IPC分类号： H03M13/23 ,  H03M13/41 ,  G06F11/10

    CPC分类号： H03M13/3961 ,  H03M13/4107

    摘要： A Viterbi decoder which operates a plurality of states at one time to thereby decode a plurality of channels at an increased speed. The decoder includes a branch metric calculating unit which receives convolutional data and calculates a plurality of branch metrics. A branch metric allocating unit allocates the plurality of branch metrics as even and odd branch metrics. A state metric storing unit stores a current state metric and allocates a plurality of state metrics as even and odd state metrics. First and second add-compare-select (ACS) units perform addition, comparison, and selection on the even branch and state metrics, and select paths having optimum distances. Third and fourth ACS units perform addition, comparison, and selection on the odd branch and state metrics, and select paths having optimum distances. A path tracing logic unit traces the path selection information selected in the first through fourth ACS units, and outputs decoded data. A path storing unit stores a path selection signal generated and selected in the path selection information controller.

    摘要翻译： 一种维特比解码器，其一次操作多个状态，从而以增加的速度解码多个信道。 解码器包括分支度量计算单元，其接收卷积数据并计算多个分支度量。 分支度量分配单元将多个分支度量分配为偶数和奇数分支度量。 状态度量存储单元存储当前状态度量，并且将多个状态度量分配为偶数和奇数状态度量。 第一和第二加 - 比选择（ACS）单元对偶分支和状态度量进行加法，比较和选择，并选择具有最佳距离的路径。 第三和第四ACS单元对奇数分支和状态度量执行加法，比较和选择，并选择具有最佳距离的路径。 路径跟踪逻辑单元跟踪在第一至第四ACS单元中选择的路径选择信息，并输出解码数据。 路径存储单元存储在路径选择信息控制器中生成和选择的路径选择信号。

    Nonvolatile memory storage system
    42.
    发明授权
    Nonvolatile memory storage system 有权

    公开(公告)号：US10229749B2

    公开(公告)日：2019-03-12

    申请号：US15475670

    申请日：2017-03-31

    申请人： Eun Chu Oh ,  Pilsang Yoon ,  Jun Jin Kong ,  Hong Rak Son ,  Dongsup Jin

    发明人： Eun Chu Oh ,  Pilsang Yoon ,  Jun Jin Kong ,  Hong Rak Son ,  Dongsup Jin

    IPC分类号： G11C29/50 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

    摘要： A nonvolatile memory storage system includes a plurality of memory cells and a memory controller configured to transmit a read command to a nonvolatile memory device based on a plurality of read voltages. The nonvolatile memory device performs a first read operation on a first level among the N levels based on a first read voltage among the plurality of read voltages, counts the number of on-cells that respond to the first read voltage among the plurality of memory cells, and adjusts a level of a second read voltage to be used to perform a second read operation on the first level or a second level among the N levels among the plurality of read voltages according to a comparison result of the counted number of on-cells and the number of reference cells.

    METHODS OF OPERATING MEMORY SYSTEMS FOR SUB-BLOCK ERASE OPERATION
    45.
    发明申请
    METHODS OF OPERATING MEMORY SYSTEMS FOR SUB-BLOCK ERASE OPERATION 有权
    操作用于子块擦除操作的存储器系统的方法

    公开(公告)号：US20160210083A1

    公开(公告)日：2016-07-21

    申请号：US15001275

    申请日：2016-01-20

    申请人： Eun Chu OH ,  Hong Rak SON ,  Jun Jin KONG ,  Seong Hyeog CHOI

    发明人： Eun Chu OH ,  Hong Rak SON ,  Jun Jin KONG ,  Seong Hyeog CHOI

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0652 ,  G06F3/0614 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

    摘要： A method of operating a memory system including memory blocks, each including memory cells and divided into at least first and second sub-blocks. The method includes performing a program operation on memory cells connected to at least one word line of the first and second sub-blocks using a first program method of programming data having a first number of bits, performing an erase operation on the first sub-block, and detecting a state of distribution of threshold voltages of memory cells of the first and second sub-blocks, and determining whether a program operation is to be performed on memory cells connected to a second adjacent word line including at least one word line adjacent to the first sub-block, out of the memory cells of the second sub-block, by using a second program method of programming data having a second number of bits, based on the detecting.

    摘要翻译： 一种操作包括存储器块的存储器系统的方法，每个存储器块包括存储器单元并被分成至少第一和第二子块。 该方法包括使用编程具有第一位数的数据的第一编程方法对连接到第一和第二子块的至少一个字线的存储器单元执行编程操作，对第一子块执行擦除操作 并且检测第一和第二子块的存储器单元的阈值电压的分布状态，并且确定是否对连接到第二相邻字线的存储器单元执行编程操作，该第二相邻字线包括与...相邻的至少一个字线 基于检测，通过使用具有第二位数的数据的第二编程方法，在第二子块的存储单元之外的第一子块。

    Semiconductor memory devices, systems including non-volatile memory read threshold voltage determination
    48.
    发明授权
    Semiconductor memory devices, systems including non-volatile memory read threshold voltage determination 有权
    半导体存储器件，系统包括非易失性存储器读取阈值电压确定

    公开(公告)号：US08817545B2

    公开(公告)日：2014-08-26

    申请号：US13404625

    申请日：2012-02-24

    申请人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

    发明人： Chang-kyu Seol ,  Jun-jin Kong ,  Hong-rak Son

    IPC分类号： G11C11/34

    CPC分类号： G06F13/1668

    摘要： A semiconductor memory system can include a memory device having a memory cell array that includes a plurality of memory cells. A memory controller can be configured to perform domain transformation on data written to and/or read from the plurality of memory cells to provide domain-transformed data and configured to perform signal processing on the domain-transformed data to output processed data or a control signal.

    摘要翻译： 半导体存储器系统可以包括具有包括多个存储单元的存储单元阵列的存储器件。 存储器控制器可以被配置为对从多个存储器单元写入和/或从多个存储器单元读取的数据执行域变换以提供域变换的数据并且被配置为对域变换的数据执行信号处理以输出处理的数据或控制信号 。

    Encoding and/or decoding memory devices and methods thereof
    49.
    发明授权
    Encoding and/or decoding memory devices and methods thereof 有权
    编码和/或解码存储器件及其方法

    公开(公告)号：US08713411B2

    公开(公告)日：2014-04-29

    申请号：US12232258

    申请日：2008-09-12

    申请人： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

    发明人： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

    IPC分类号： H03M13/00

    CPC分类号： H03M13/03 ,  G06F11/1072 ,  H03M13/05

    摘要： Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.

    摘要翻译： 可以提供编码/解码存储器件及其方法。 根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。 处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。 可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。 因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。