公开(公告)号：US20090302416A1

公开(公告)日：2009-12-10

申请号：US12135242

申请日：2008-06-09

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

IPC: H01L23/525 ,  H01L21/44

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

Abstract translation: 本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由 阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。 通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

公开(公告)号：US20090179267A1

公开(公告)日：2009-07-16

申请号：US12013101

申请日：2008-01-11

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

IPC: H01L27/12 ,  H01L21/786

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.

Abstract translation: 高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。 栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将每个栅电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

公开(公告)号：US20090089719A1

公开(公告)日：2009-04-02

申请号：US12127245

申请日：2008-05-27

Applicant: Robert J. Gauthier, JR. ,  Junjun Li

Inventor： Robert J. Gauthier, JR. ,  Junjun Li

IPC: H02H9/00 ,  G06F17/50

CPC classification number: G06F17/5045 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

Abstract translation: 用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

公开(公告)号：US20080237721A1

公开(公告)日：2008-10-02

申请号：US11692481

申请日：2007-03-28

Applicant: Michel J. Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Michel J. Abou-Khalil ,  Robert Gauthier ,  Hongmei Li ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H01L23/60

CPC classification number: H01L27/0277 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An external current injection source is provided to individual fingers of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source is adjusted so that each finger has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.

Abstract translation: 外部电流注入源被提供给多指半导体器件的各个指状物，以跨多个指状物提供相同的触发电压。 例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。 调整来自每个外部电流注入源的供给电流的大小，使得每个手指具有相同的触发电压。 外部电流供应电路可以包括二极管或RC触发MOSFET。 可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

公开(公告)号：US20070285853A1

公开(公告)日：2007-12-13

申请号：US11422608

申请日：2006-06-07

Applicant: Robert J. Gauthier ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

Inventor： Robert J. Gauthier ,  Dimitrios K. Kontos ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An electrostatic discharge (ESD) power clamp circuit including a RC-delay element coupled to a plurality of serialized inverter elements with a power clamp element and an ESD-triggered keeper device coupled to the plurality of inverters. During negative mode ESD events, the ESD-triggered keeper device is activated and assists the power clamp element to pull up and strongly conduct current to protect the circuit. Additionally, a method of ESD protection in a circuit is provided. The method includes coupling a RC-delay element to an input of a plurality of serialized inverter elements, coupling an output of the plurality of serialized inverters with an ESD-triggered keeper device and a power clamp element, triggering the ESD-triggered keeper device to turn on during negative ESD events and conducting current by the power clamp element with assistance of the ESD-triggered keeper device to protect the circuit as a result of negative ESD events.

Abstract translation: 一种静电放电（ESD）功率钳位电路，其包括耦合到多个串联反相器元件的RC延迟元件，其具有耦合到所述多个逆变器的功率钳位元件和ESD触发的保持器装置。 在负模式ESD事件期间，ESD触发的保护装置被激活，并且帮助电源钳位元件上拉并强烈地传导电流以保护电路。 另外，提供了电路中ESD保护的方法。 该方法包括将RC延迟元件耦合到多个串联反相器元件的输入端，将多个串联反相器的输出与ESD触发的保持器装置和功率钳位元件耦合，将ESD触发的保持器装置触发 在ESD ESD事件期间接通电源，并通过ESD触发的保护装置的辅助，通过电源钳位元件传导电流，以保护电路由于负ESD事件。

公开(公告)号：US07298008B2

公开(公告)日：2007-11-20

申请号：US11275638

申请日：2006-01-20

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A. Mousa ,  Christopher Stephen Putnam

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/7436 ,  H01L21/84 ,  H01L27/0262 ,  H01L27/1203

Abstract: Disclosed are a silicon control rectifier, a method of making the silicon control rectifier and the use of the silicon control rectifier as an electrostatic discharge protection device of an integrated circuit. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract translation: 公开了一种硅控制整流器，制造硅控制整流器的方法和使用硅控整流器作为集成电路的静电放电保护器件。 硅控制整流器包括形成在硅层中的硅体，其与绝缘体上硅衬底的掩埋氧化物层直接物理接触，硅层的顶表面限定水平面; 并且形成在硅体的第一区域中的硅控制整流器的阳极和形成在硅体的相对的第二区域中的硅控制整流器的阴极，其中阳极和阴极之间的电流路径仅为 在平行于水平面的单个水平方向上。

公开(公告)号：US20060039093A1

公开(公告)日：2006-02-23

申请号：US10711085

申请日：2004-08-20

Applicant: Robert Gauthier, Jr. ,  Junjun Li

Inventor： Robert Gauthier, Jr. ,  Junjun Li

IPC: H02H9/00

CPC classification number: H01L27/0266

Abstract: An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.

Abstract translation: 用于抑制ESD事件的ESD保护电源钳。 具有连接在集成电路的电源端子上的电源连接的钳位晶体管被连接以在ESD事件期间钳位电压。 RC定时电路定义用于触发FET导通的ESD电压的时间间隔。 逆变器电路将RC和定时电路连接到钳位FET。 动态反馈晶体管与逆变器和电源的一级串联连接。 在ESD事件期间，反馈晶体管延迟了禁止FET晶体管的时间，提供了抵抗钳位晶体管失谐的增强的抗扰性，并迫使电路在雾触发器事件之后复位。

公开(公告)号：US09219056B2

公开(公告)日：2015-12-22

申请号：US13431347

申请日：2012-03-27

Applicant: William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li

Inventor： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Junjun Li

IPC: H01L27/06 ,  H01L21/20 ,  H01L21/33 ,  H01L27/02 ,  H01L21/8249 ,  H01L21/84 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L27/0262 ,  G06F17/5072 ,  H01L21/8249 ,  H01L21/845 ,  H01L27/0255 ,  H01L27/06 ,  H01L27/1211 ,  H01L29/06

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract translation: 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 将绝缘体上半导体衬底的器件层的一部分图案化以形成器件区域。 在外延层和器件区域中形成第一导电类型的阱。 在阱中形成第二导电类型的掺杂区域并且限定与阱的一部分的结。 外延层包括与器件区域的外侧壁间隔开的外侧壁。 可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US09058995B2

公开(公告)日：2015-06-16

申请号：US13440514

申请日：2012-04-05

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

IPC: H01L21/00 ,  H01L29/66 ,  H01L27/02 ,  H01L29/74 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/027 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/7436 ,  H01L29/7824 ,  H01L29/7835

Abstract: Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well.

Abstract translation: 漏极延伸金属氧化物半导体（DEMOS）晶体管的器件结构，设计结构和制造方法。 第一导电类型的第一阱和第二导电类型的第二阱形成在器件区域中。 第一和第二井并列以定义p-n结。 第一导电类型的第一掺杂区域和第二导电类型的掺杂区域位于第一阱中。 第一导电类型的第一掺杂区域与第一阱的第一部分与第二阱分离。 第二导电类型的掺杂区域与第一阱的第二部分与第二阱分离。 在第二阱中的第一导电类型的第二掺杂区域由第一阱的第一和第二部分的第二阱的一部分分开。

公开(公告)号：US08815654B2

公开(公告)日：2014-08-26

申请号：US11762811

申请日：2007-06-14

Applicant: Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A Mousa ,  Christopher S. Putnam

Inventor： Robert J. Gauthier, Jr. ,  Junjun Li ,  Souvick Mitra ,  Mahmoud A Mousa ,  Christopher S. Putnam

IPC: H01L21/84 ,  H01L27/02

CPC classification number: H01L27/0262

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract translation: 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片及其制造方法 s）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。