公开(公告)号：US20130084654A1

公开(公告)日：2013-04-04

申请号：US13250960

申请日：2011-09-30

申请人： Richard H. Gaylord ,  Blaze J. Messer ,  Kaushik A. Kumar

发明人： Richard H. Gaylord ,  Blaze J. Messer ,  Kaushik A. Kumar

IPC分类号： H01L21/66 ,  H01L21/3065

CPC分类号： H01L21/31116 ,  H01L21/02057 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device. A substrate having first and second materials is provided, wherein the second material is occluded by the first material. The substrate is etched using a first non-plasma etch process that etches the first material at a higher rate relative to a rate of etching the second material. The first non-plasma etch process exposes the second material that is overlying at least a portion of the first material. The second material is then etched using a plasma containing a reactive gas, which exposes the at least a portion of the first material. The first material including the at least a portion of the first material that was exposed by etching the second material are etched using a second non-plasma etch process.

摘要翻译： 一种形成半导体器件的方法。 提供了具有第一和第二材料的基板，其中第二材料被第一材料遮挡。 使用第一非等离子体蚀刻工艺蚀刻衬底，相对于蚀刻第二材料的速率，蚀刻第一材料的速率更高。 第一非等离子体蚀刻工艺暴露了覆盖第一材料的至少一部分的第二材料。 然后使用包含暴露第一材料的至少一部分的反应性气体的等离子体来蚀刻第二材料。 使用第二非等离子体蚀刻工艺蚀刻包括通过蚀刻第二材料而暴露的第一材料的至少一部分的第一材料。

公开(公告)号：US20100133694A1

公开(公告)日：2010-06-03

申请号：US12701045

申请日：2010-02-05

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L23/48 ,  H01L23/498

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了包括金属互连的金属互连和IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。

公开(公告)号：US07718525B2

公开(公告)日：2010-05-18

申请号：US11770928

申请日：2007-06-29

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了形成金属互连的方法和包括金属互连的IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。

公开(公告)号：US07696025B2

公开(公告)日：2010-04-13

申请号：US11867840

申请日：2007-10-05

申请人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence A. Clevenger ,  Omer H. Dokumaci ,  Kaushik A. Kumar ,  Carl J. Radens ,  Dureseti Chidambarrao

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/1083 ,  H01L29/66795

摘要： A novel transistor structure and method for fabricating the same. First, a substrate, a semiconductor region, a gate dielectric region, and a gate block are provided. The semiconductor region, the gate dielectric region, and the gate block are on the substrate. The gate dielectric region is sandwiched between the semiconductor region and the gate block. The semiconductor region is electrically insulated from the gate block by the gate dielectric region. The semiconductor region and the gate dielectric region share an interface surface which is essentially perpendicular to a top surface of the substrate. The semiconductor region and the gate dielectric region do not share any interface surface that is essentially parallel to a top surface of the substrate. Next, a gate region is formed from the gate block. Then, first and second source/drain regions are formed in the semiconductor region.

摘要翻译： 一种新颖的晶体管结构及其制造方法。 首先，提供衬底，半导体区域，栅极介质区域和栅极块。 半导体区域，栅极电介质区域和栅极块在衬底上。 栅极电介质区域夹在半导体区域和栅极块之间。 半导体区域通过栅极电介质区域与栅极块电绝缘。 半导体区域和栅极电介质区域共享基本上垂直于衬底顶表面的界面。 半导体区域和栅极介电区域不共享基本上平行于衬底顶表面的任何界面表面。 接下来，从栅极块形成栅极区域。 然后，在半导体区域中形成第一和第二源极/漏极区域。

公开(公告)号：US07629264B2

公开(公告)日：2009-12-08

申请号：US12099996

申请日：2008-04-09

申请人： Griselda Bonilla ,  Kaushik A. Kumar ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Kevin S. Petrarca ,  Roger A. Quon

发明人： Griselda Bonilla ,  Kaushik A. Kumar ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Kevin S. Petrarca ,  Roger A. Quon

IPC分类号： H01L21/302

CPC分类号： H01L23/5329 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/76835 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu).

摘要翻译： 本发明在一个实施例中提供了一种形成互连的方法，包括：在衬底顶部提供层间电介质层，所述层间电介质层包括从层间电介质的上表面延伸到衬底的至少一个钨（W）柱; 将所述至少一个钨（W）螺柱的上表面凹陷在所述层间电介质的上表面下方，以提供至少一个凹入的钨（W）螺柱; 在所述层间介电层的上表面和所述至少一个凹入的钨（W）螺柱之上形成第一低k电介质层; 通过所述第一低k电介质层形成开口以露出所述至少一个凹入的钨螺柱的上表面; 并用铜（Cu）填充开口。

公开(公告)号：US20090256263A1

公开(公告)日：2009-10-15

申请号：US12099996

申请日：2008-04-09

申请人： Griselda Bonilla ,  Kaushik A. Kumar ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Kevin S. Petrarca ,  Roger A. Quon

发明人： Griselda Bonilla ,  Kaushik A. Kumar ,  Lawrence A. Clevenger ,  Stephan Grunow ,  Kevin S. Petrarca ,  Roger A. Quon

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5329 ,  H01L21/76804 ,  H01L21/76819 ,  H01L21/76835 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention in one embodiment provides a method of forming an interconnect comprising, providing a interlevel dielectric layer atop a substrate, the interlevel dielectric layer including at least one tungsten (W) stud extending from an upper surface of the interlevel dielectric to the substrate; recessing an upper surface of the at least one tungsten (W) stud below the upper surface of the interlevel dielectric to provide at least one recessed tungsten (W) stud; forming a first low-k dielectric layer atop the upper surface of the interlevel dielectric layer and the at least one recessed tungsten (W) stud; forming a opening through the first low-k dielectric layer to expose an upper surface of the at least one recessed tungsten stud; and filling the opening with copper (Cu).

摘要翻译： 本发明在一个实施例中提供了一种形成互连的方法，包括：在衬底顶部提供层间电介质层，所述层间电介质层包括从层间电介质的上表面延伸到衬底的至少一个钨（W）柱; 将所述至少一个钨（W）螺柱的上表面凹陷在所述层间电介质的上表面下方，以提供至少一个凹入的钨（W）螺柱; 在所述层间介电层的上表面和所述至少一个凹入的钨（W）螺柱之上形成第一低k电介质层; 通过所述第一低k电介质层形成开口以露出所述至少一个凹入的钨螺柱的上表面; 并用铜（Cu）填充开口。

公开(公告)号：US20090085210A1

公开(公告)日：2009-04-02

申请号：US11863724

申请日：2007-09-28

申请人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

发明人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/522 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00

摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

摘要翻译： 半导体结构及其形成方法。 该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。 该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。 该结构还包括第一ILD层中的第一沟槽。 第一条沟没有完全填满固体材料。 如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的 跨越第一ILD层的金属线的图案密度。

公开(公告)号：US07456099B2

公开(公告)日：2008-11-25

申请号：US11420253

申请日：2006-05-25

申请人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Vidhya Ramachandran ,  Theodorus E. Standaert

发明人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Vidhya Ramachandran ,  Theodorus E. Standaert

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a plurality of conductive lines formed within an interlevel dielectric (ILD) layer and a non-planar cap layer formed over the ILD layer and the conductive lines, wherein the cap layer is raised with respect to the conductive lines at locations between the conductive lines.

摘要翻译： 半导体结构包括形成在层间电介质（ILD）层内的多个导电线和形成在ILD层和导电线之上的非平面覆盖层，其中覆盖层相对于导电线在第 导线。

公开(公告)号：US20080254612A1

公开(公告)日：2008-10-16

申请号：US12140854

申请日：2008-06-17

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, O≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8，O <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.8; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US07396758B2

公开(公告)日：2008-07-08

申请号：US11619502

申请日：2007-01-03

申请人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

发明人： Elbert E. Huang ,  Kaushik A. Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy S. Tyberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.08; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。