Pipelines for secure multithread execution

    公开(公告)号:US11886882B2

    公开(公告)日:2024-01-30

    申请号:US17713744

    申请日:2022-04-05

    IPC分类号: G06F9/38 H04L9/06 G06F9/48

    摘要: Described herein are systems and methods for secure multithread execution. For example, some methods include fetching an instruction of a first thread from a memory into a processor pipeline that is configured to execute instructions from two or more threads in parallel using execution units of the processor pipeline; detecting that the instruction has been designated as a sensitive instruction; responsive to detection of the sensitive instruction, disabling execution of instructions of threads other than the first thread in the processor pipeline during execution of the sensitive instruction by an execution unit of the processor pipeline; executing the sensitive instruction using an execution unit of the processor pipeline; and, responsive to completion of execution of the sensitive instruction, enabling execution of instructions of threads other than the first thread in the processor pipeline.

    Efficient signaling scheme for high-speed ultra short reach interfaces

    公开(公告)号:US11880321B2

    公开(公告)日:2024-01-23

    申请号:US17521612

    申请日:2021-11-08

    发明人: Ramin Farjadrad

    IPC分类号: G06F13/36 H04L7/00 H04L25/20

    摘要: A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.

    Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor

    公开(公告)号:US11874896B2

    公开(公告)日:2024-01-16

    申请号:US17119796

    申请日:2020-12-11

    IPC分类号: G06F17/14 G06F17/16 H04W16/18

    摘要: Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In an exemplary embodiment, a method includes receiving a plurality of discrete Fourier transform (DFT) jobs. Each job identifies a computation of a DFT of a particular point size. The method also includes bundling selected jobs having a selected point size into a mega-job, and identifying a radix factorization for the selected point size. The radix factorization includes one or more stages and each stage identifies a radix computation to be performed. The method also includes computing, for each stage, the identified radix computations for the selected jobs in the mega-job. The radix computations for each stage are performed for the selected jobs before performing radix computations for a subsequent stage. The method also includes outputting DFT results for the selected jobs in the mega-job.

    Gate stack for metal gate transistor

    公开(公告)号:US11862453B2

    公开(公告)日:2024-01-02

    申请号:US17445965

    申请日:2021-08-26

    发明人: Runzi Chang

    摘要: Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.

    PHYSICAL LAYER FRAME FORMAT FOR WLAN
    48.
    发明公开

    公开(公告)号:US20230421295A1

    公开(公告)日:2023-12-28

    申请号:US18244792

    申请日:2023-09-11

    摘要: A preamble of physical layer (PHY) data unit includes a first legacy portion and a first non-legacy portion that follows the first legacy portion. The first non-legacy portion includes i) a first orthogonal frequency division multiplexing (OFDM) symbol that immediately follows the first legacy portion and that is modulated using binary phase shift keying (BPSK), and ii) a second OFDM symbol that immediately follows the first OFDM symbol and that is modulated using BPSK modulation rotated by 90 degrees (Q-BPSK). The modulation of the first and second OFDM symbols indicates to a receiver device that conforms to a first communication protocol that the data unit conforms to the first communication protocol. The first OFDM symbol being modulated using BPSK modulation causes a receiver device that conforms to a second communication protocol to determine that the PHY data unit conforms to a third communication protocol.

    Lossless integer compression scheme

    公开(公告)号:US11854235B1

    公开(公告)日:2023-12-26

    申请号:US17197268

    申请日:2021-03-10

    发明人: Tao Lu

    摘要: Decompressing a compressed image to obtain a decompressed image includes receiving, in a compressed stream, compressed pixel values of the compressed image; decompressing, from the compressed stream, a first compressed pixel value of the compressed pixel values using a lossy floating-point decompression scheme to obtain a floating-point pixel value; rounding the floating-point pixel value to a nearest integer to obtain a pixel value of the decompressed image; and displaying or storing the decompressed image.