公开(公告)号：US20030222355A1

公开(公告)日：2003-12-04

申请号：US10445040

申请日：2003-05-27

Applicant: NEC ELECTRONICS CORPORATION

Inventor： Yoshihiro Masumura ,  Nobuteru Oh ,  Hiroyuki Furukawa

IPC: H01L023/48

CPC classification number: H01L27/0203 ,  H01L22/32 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an internal circuit area including a plurality of I/O modules, and a peripheral area receiving therein a pair of loop test lines for testing I/O buffers in the I/O modules. The internal test line extending from each of the loop test lines toward the internal circuit area includes an out-module test line formed as the topmost layer, a first in-module test line formed as the topmost layer and connected to the out-module test line, and a second in-module test line, a portion of which is formed by connecting the in-buffer test lines together.

Abstract translation: 半导体器件包括包括多个I / O模块的内部电路区域和在其中接收用于测试I / O模块中的I / O缓冲器的一对环路测试线的外围区域。 从每个环路测试线向内部电路区域延伸的内部测试线包括形成为最上层的外部模块测试线，形成为最上层的第一模块内测试线并连接到模块外测试 线和第二模块内测试线，其一部分通过将缓冲区内测试线连接在一起形成。

公开(公告)号：US20030214343A1

公开(公告)日：2003-11-20

申请号：US10436151

申请日：2003-05-13

Applicant: NEC ELECTRONICS CORPORATION

Inventor： Fumihiko Kato

IPC: G06F001/00

CPC classification number: H03K17/693 ,  H03K17/6872 ,  H03K2217/0018

Abstract: A gradation selector circuit provided with a resistor string circuit in which resistive elements are connected in series between a high potential power source and a low potential power source and a selector circuit which is connected to the resistor string circuit, which selects one of plural analog voltages generated in the resistor string circuit according to a control signal and which outputs it to an output terminal is used. The selector circuit includes analog switching circuits that select analog voltage close to intermediate potential. The analog switching circuit includes a P-type MOS transistor to the source electrode and the back gate electrode of which the resistor string circuit is connected and a depletion type N-type MOS transistor to the source electrode of which the drain electrode of the P-type MOS transistor is connected and to the drain electrode of which an output terminal is connected.

Abstract translation: 一种灰度选择器电路，其设置有电阻串电路，其中电阻元件串联连接在高电位电源和低电位电源之间，选择电路连接到电阻串电路，其选择多个模拟电压 根据控制信号在电阻串电路中产生并将其输出到输出端子。 选择器电路包括选择接近中间电位的模拟电压的模拟开关电路。 模拟开关电路包括一个P型MOS晶体管，源极电极和连接电阻串电路的背栅电极和一个耗尽型N型MOS晶体管连接到源电极，其中P- 连接MOS晶体管和连接输出端子的漏电极。

公开(公告)号：US20030211640A1

公开(公告)日：2003-11-13

申请号：US10431612

申请日：2003-05-08

Applicant: NEC Electronics Corporation

Inventor： Junji Orimoto

IPC: H01L021/00 ,  H01L021/66 ,  G01R031/26 ,  H01L021/64

CPC classification number: H01L21/67253 ,  G05B19/41865 ,  G05B2219/32019 ,  G05B2219/32097 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/20

Abstract: A system is provided for maintaining plural different process flows for manufacturing different kinds of semiconductor device respectively on a semiconductor production line. The plural different process flows are registered in an automatic process control system. The system includes a function unit for setting an automatic process control in the automatic process control system based on an automatic process control information for each of the plural different process. The automatic control information for each of the plural different process flows further includes a process flow name, and process names respectively unique to the single process flow.

Abstract translation: 提供了一种用于在半导体生产线上分别制造用于制造不同种类的半导体器件的多个不同工艺流程的系统。 多个不同的处理流程被登记在自动过程控制系统中。 该系统包括用于基于用于多个不同处理中的每一个的自动处理控制信息在自动处理控制系统中设置自动处理控制的功能单元。 多个不同处理流程中的每一个的自动控制信息还包括分别对于单个处理流程唯一的处理流程名称和处理名称。

公开(公告)号：US20030209760A1

公开(公告)日：2003-11-13

申请号：US10424938

申请日：2003-04-29

Applicant: NEC ELECTRONICS CORPORATION

Inventor： Shinya Maruyama

IPC: H01L027/01

CPC classification number: H01L21/76264 ,  H01L21/76283

Abstract: An SOI (Silicon On Insulator) wafer which has a BOX (Buried Oxide) layer and an SOI layer formed on a silicon substrate is prepared. A silicon oxide film and a silicon nitride film are deposited and patterned on the surface of the SOI layer. Then, with the silicon oxide film and silicon nitride film used as masks, dry etching is performed to form trenches, which do not reach the BOX layer, in the SOI layer. Next, round oxidation is executed by performing thermal oxidation on the SOI wafer, thereby forming a silicon oxide film in that region of the SOI layer which corresponds to the bottom and sides of each trench. Then, with a photoresist as a mask, the SOI layer which is located at the bottoms of the trenches is selectively etched out to form trenches which reach the BOX layer. Then, an STI (Shallow Trench Isolation) region is formed in those trenches.

Abstract translation: 准备在硅衬底上形成有BOX（掩埋氧化物）层和SOI层的SOI（绝缘体上硅）晶片。 氧化硅膜和氮化硅膜在SOI层的表面上沉积和图案化。 然后，在氧化硅膜和氮化硅膜用作掩模的情况下，进行干法蚀刻，以在SOI层中形成不到BOX层的沟槽。 接下来，通过在SOI晶片上进行热氧化来进行圆形氧化，从而在对应于每个沟槽的底部和侧面的SOI层的区域中形成氧化硅膜。 然后，以光致抗蚀剂为掩模，选择性地蚀刻位于沟槽底部的SOI层，形成到达BOX层的沟槽。 然后，在这些沟槽中形成STI（浅沟槽隔离）区域。

公开(公告)号：US20030209323A1

公开(公告)日：2003-11-13

申请号：US10427918

申请日：2003-05-02

Applicant: NEC Electronics Corporation

Inventor： Tsuyoshi Yokogaki

IPC: H01L021/306 ,  C23C016/00

CPC classification number: C23C16/45565 ,  C23C16/455

Abstract: The present invention discloses a production apparatus for manufacturing semiconductor device which comprises a vacuum processing chamber where film formation or etching is performed for a semiconductor wafer, a gas introducing part for introducing a process gas into the vacuum processing chamber, and a shower head for uniformly diffusing the introduced process gas, where a plate having a plurality of gas blowing holes for blowing the process gas on the semiconductor wafer are arranged and opened with uniform density is provided on the face of a shower head opposing the semiconductor wafer. Each of the gas blowing holes opened in the plate is a steeped hole having a large diameter hole part and a small diameter hole part, formed by varying the step location in response to the pressure distribution of the process gas within the shower head so as to make the amount of the gas blown from respective gas blowing holes uniform.

Abstract translation: 本发明公开了一种半导体装置的制造装置，其特征在于，包括对半导体晶片进行成膜或蚀刻的真空处理室，将真空处理室内的工序气体导入的气体导入部， 扩散引入的处理气体，其中在与半导体晶片相对的喷淋头的表面上设置有具有用于吹制半导体晶片上的处理气体的多个气体吹扫孔的板以均匀的密度布置和打开的板。 在板上开放的每个气体吹入孔是具有大直径孔部分和小直径孔部分的浸泡孔，其响应于淋浴喷头内的处理气体的压力分布而改变台阶位置而形成，从而 使得从各个气体吹入孔吹出的气体的量均匀。

公开(公告)号：US20030204832A1

公开(公告)日：2003-10-30

申请号：US10423069

申请日：2003-04-25

Applicant: NEC Electronics Corporation

Inventor： Akira Matumoto

IPC: G06F017/50 ,  G06F009/455

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: An automatic generation method of dummy patterns of the present invention includes: a first step of preparing a plurality of dummy pattern components which have regularly arranged dummy patterns, respectively, and for which priorities are set based upon a predetermined rule; a second step of selecting one of the plurality of dummy pattern components and arranging dummy patterns belonging to the selected dummy pattern component to overlap layout data of mask patterns for which arrangement prohibition regions are set; a third step of deleting dummy patterns which are in contact with or overlap the arrangement prohibition regions among the arranged dummy patterns; and a fourth step of deleting dummy patterns belonging to the dummy pattern component with a lower priority in the case in which a plurality of dummy patterns are in contact with or overlap each other.

Abstract translation: 本发明的虚拟图案的自动生成方法包括：第一步骤，准备分别具有规则排列的虚拟图案的多个虚拟图案组件，并且基于预定规则设定优先级; 选择所述多个虚拟图案组分中的一个并且排列属于所选择的虚拟图案分量的虚拟图案以重叠设置了布置禁止区域的掩模图案的布局数据的第二步骤; 第三步骤，在布置的虚拟图案中删除与布置禁止区域接触或重叠的虚拟图案; 以及第四步骤，在多个虚设图案相互接触或重叠的情况下，以较低的优先级删除属于该虚拟图案组件的虚拟图案。

公开(公告)号：US20030204340A1

公开(公告)日：2003-10-30

申请号：US10420753

申请日：2003-04-23

Applicant: NEC ELECTRONICS CORPORATION

Inventor： Kazuo Ootouge

IPC: G06F019/00 ,  G01R021/00 ,  G01R021/06

CPC classification number: G06F17/5036 ,  G06F17/5022

Abstract: There is provided a power supply voltage fluctuation analyzing method which performs power supply voltage fluctuation analysis for a semiconductor product, and the method comprises a step of determining a power consumption distribution in each function cell of the semiconductor product by using a power supply portion position and a ratio of each portion based on stored information of an input library which stores therein the power supply portion position and ratio information for each function cell of the semiconductor product, and allocating a power consumption to each function cell.

Abstract translation: 提供了对半导体产品进行电源电压波动分析的电源电压波动分析方法，该方法包括以下步骤：通过使用电源部位置来确定半导体产品的各个功能单元的功耗分布;以及 基于其中存储有半导体产品的每个功能单元的电源部分位置和比率信息的输入库的存储信息的每个部分的比率，并且将功耗分配给每个功能单元。

公开(公告)号：US20030201484A1

公开(公告)日：2003-10-30

申请号：US10421482

申请日：2003-04-23

Applicant: NEC Electronics Corporation

Inventor： Ken Ozawa

IPC: H01L027/108

CPC classification number: H01L28/40 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor capacitor configured so as to use buried wirings, as electrodes, formed in an interlayer dielectric is provided on a semiconductor substrate which is capable of preventing an increase in a number of manufacturing processes with occurrence of parasitic capacity being suppressed. The semiconductor capacitor has a capacitive insulating film made up of an etching stopper film formed only in a region being sandwiched between a via plug serving as an upper electrode and a lower electrode, in which the capacitive insulating film is not formed in a region other than the facing region.

Abstract translation: 在半导体基板上设置半导体电容器，该半导体电容器被构造为使用形成在层间电介质中的作为电极的埋入布线，其能够防止在抑制寄生电容的发生的情况下增加制造工艺。 半导体电容器具有电容绝缘膜，该电容绝缘膜仅由夹在用作上电极的通孔和下电极之间形成的区域中形成，其中电容绝缘膜不形成在除了 面对地区。

公开(公告)号：US20030199145A1

公开(公告)日：2003-10-23

申请号：US10420982

申请日：2003-04-22

Applicant: NEC Electronics Corporation

Inventor： Akira Noguchi

IPC: H01L021/66 ,  H01L021/336

CPC classification number: H01L29/66477 ,  H01L21/324

Abstract: Disclosed is a method for correcting a transistor of a predetermined threshold value. According to the method, after preparing a gate 13 of the transistor, depending on how well the gate is prepared, a threshold voltage Vth showing transistor characteristic is corrected by adjusting an oxygen concentration of a lamp-annealing step 21, which is to be performed subsequently. Moreover, disclosed is a method for fabricating a transistor of a predetermined threshold value. According to the method, after preparing the gate 13 of the transistor, the threshold voltage Vth showing the transistor characteristic is predicted or measured. When the threshold voltage deviates from the predetermined value, the oxygen concentration is adjusted in the lamp-annealing step 21 of the transistor that is to be fabricated subsequently and thus the threshold value is set to the predetermined value without lowered reliability due to the damage of the gate oxide film and without additional process steps.

Abstract translation: 公开了一种用于校正预定阈值的晶体管的方法。 根据该方法，在准备晶体管的栅极13之后，取决于栅极的准备情况，通过调整要执行的灯退火步骤21的氧浓度来校正显示晶体管特性的阈值电压Vth 后来。 此外，公开了一种用于制造预定阈值的晶体管的方法。 根据该方法，在准备晶体管的栅极13之后，预测或测量表示晶体管特性的阈值电压Vth。 当阈值电压偏离预定值时，在随后要制造的晶体管的灯退火步骤21中调节氧浓度，因此阈值被设置为预定值，而不会由于损坏而导致可靠性降低 栅极氧化膜并且没有额外的工艺步骤。

公开(公告)号：US20030198896A1

公开(公告)日：2003-10-23

申请号：US10408317

申请日：2003-04-08

Applicant: NEC ELECTRONICS CORPORATION

Inventor： Masashi Fujimoto

IPC: G03F007/16 ,  G03F007/40

CPC classification number: H01L21/76808 ,  H01L2221/1036

Abstract: A via hole 18 is opened in an interlayer insulating film 17, which covers a lower layer interconnect 12, a protective film 19 is embedded on the base portion of the via hole 18, and a soluble resin 20, which dissolves in a resist developing fluid under unexposed conditions, is further embedded thereupon. On this basis, a photoresist 21 is applied, and this photoresist 21 is subjected to an exposure and a development process so as to form a resist pattern 21a, which has an aperture window in a region including the via hole. Upon formation of an interconnective trench in the interlayer insulating film 17 utilizing the resist pattern 21a, a dual damascene structure is formed by embedding a metallic material into the vial hole and interconnective trench.

Abstract translation: 通孔18在覆盖下层布线12的层间绝缘膜17中开口，保护膜19嵌入在通孔18的基部上，溶解树脂20溶解在抗蚀剂显影液 在未曝光的条件下，进一步嵌入其中。 在此基础上，施加光致抗蚀剂21，并对该光致抗蚀剂21进行曝光和显影处理，以形成在包括通孔的区域中具有孔眼的抗蚀剂图案21a。 在利用抗蚀剂图案21a的层间绝缘膜17中形成互连沟槽时，通过将金属材料嵌入小瓶孔和互连沟槽中形成双镶嵌结构。