公开(公告)号：US20070161205A1

公开(公告)日：2007-07-12

申请号：US11556170

申请日：2006-11-03

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L21/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US20070161179A1

公开(公告)日：2007-07-12

申请号：US11321156

申请日：2005-12-28

申请人： Pei-Ing Lee

发明人： Pei-Ing Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10835 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10891

摘要： A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines are formed across the recessed gates. Bit lines are formed to electrically connect the buried bit line contacts without crossing the capacitor buried surface straps, and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.

摘要翻译： 提供一种形成半导体器件的方法。 该方法包括在其中提供具有凹入栅极的衬底和其中的深沟槽电容器器件。 显露了深沟槽电容器器件的凹入栅极和上部的突出。 间隔件形成在上部和突起的侧壁上。 导电材料的埋入部分形成在间隔件之间的空间中。 将衬底，间隔物和掩埋部分图案化以形成用于限定掩埋位线接触和电容器埋入表面带的平行浅沟槽。 在浅沟槽中形成介电材料层。 字线形成在凹入的门之间。 位线被形成为电连接掩埋位线触点而不与电容器埋入表面带交叉，并且形成堆叠电容器以与电容器埋入表面带电连接。 还提供了半导体器件。

公开(公告)号：US07179748B1

公开(公告)日：2007-02-20

申请号：US11195293

申请日：2005-08-02

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/311

CPC分类号： H01L21/3086 ,  H01L21/26586 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L29/66621 ,  Y10S438/944 ,  Y10S438/947

摘要： A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer with a first angle using a first implanting mask adjacent to the first side wall of the protrusions, tilt implanting the mask layer with a second angle using a second implanting mask adjacent to the second side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess, wherein distances from the recess to the two protrusions, respectively, are different.

摘要翻译： 一种形成凹部的方法。 该方法包括提供具有两个突出物的两个突起，所述两个突起具有第一侧壁和与设置在基底上方的第一侧壁相对的第二侧壁，在基底上共形成掩模层和突起，倾斜地将掩模层以第一 使用与突起的第一侧壁相邻的第一注入掩模的角度，使用与突起的第二侧壁相邻的第二注入掩模以第二角度注入掩模层，去除掩模层的植入部分以形成 图案化掩模层，并使用图案化掩模层蚀刻基板，从而形成凹部，其中分别从凹部到两个突起的距离不同。

公开(公告)号：US20060270176A1

公开(公告)日：2006-11-30

申请号：US11140889

申请日：2005-05-31

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/20

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a semiconductor device. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 一种形成半导体器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。

公开(公告)号：US20060270151A1

公开(公告)日：2006-11-30

申请号：US11145728

申请日：2005-06-06

申请人： Pei-Ing Lee

发明人： Pei-Ing Lee

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried bit line contacts. Word lines are formed across the recessed gates, wherein at least one of the word lines comprises portions overlapping the recessed gates. At least one of the overlapped portions has a narrower width than at least one of the recessed gates.

摘要翻译： 一种形成半导体器件的方法。 提供了一种衬底，其中衬底在其中具有凹入栅极和深沟槽电容器器件。 显露了深沟槽电容器器件的凹入栅极和上部的突出。 间隔件形成在上部和突起的侧壁上。 导电材料的埋入部分形成在间隔件之间的空间中。 将衬底，间隔物和掩埋部分图案化以形成用于限定有源区域的平行的浅沟槽。 在浅沟槽中形成介电材料层，其中一些掩埋部分用作掩埋位线接触。 字线形成在凹入的栅极之间，其中至少一个字线包括与凹入栅极重叠的部分。 重叠部分中的至少一个具有比凹入栅极中的至少一个更窄的宽度。

公开(公告)号：US20060270150A1

公开(公告)日：2006-11-30

申请号：US11145585

申请日：2005-06-06

申请人： Pei-Ing Lee

发明人： Pei-Ing Lee

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions to form parallel shallow trenches are patterned to form parallel shallow trenches for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried contacts.

摘要翻译： 一种形成半导体器件的方法。 提供了一种衬底，其中衬底在其中具有凹入栅极和深沟槽电容器器件。 显露了深沟槽电容器器件的凹入栅极和上部的突出。 间隔件形成在上部和突起的侧壁上。 导电材料的埋入部分形成在间隔件之间的空间中。 图案化衬底，间隔物和形成平行的浅沟槽的掩埋部分以形成用于限定活性区域的平行的浅沟槽。 在浅沟槽中形成介电材料层，其中一些掩埋部分用作掩埋触点。

公开(公告)号：US06403483B1

公开(公告)日：2002-06-11

申请号：US09695144

申请日：2000-10-25

申请人： Chung-Peng Hao ,  Chung-Lin Huang ,  Chung-Yuan Lee ,  Yih-Ren Shao ,  Pei-Ing Lee

发明人： Chung-Peng Hao ,  Chung-Lin Huang ,  Chung-Yuan Lee ,  Yih-Ren Shao ,  Pei-Ing Lee

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/76224

摘要： A shallow trench isolation having an etching stop layer and its method of fabrication. The method utilizes a shield layer such as a silicon nitride layer to serve as an etching stop layer. The etching stop layer is formed in the top position of the shallow trench isolation.

摘要翻译： 具有蚀刻停止层的浅沟槽隔离及其制造方法。 该方法利用诸如氮化硅层的屏蔽层作为蚀刻停止层。 蚀刻停止层形成在浅沟槽隔离的顶部位置。