公开(公告)号：US20080026531A1

公开(公告)日：2008-01-31

申请号：US11684211

申请日：2007-03-09

Applicant: Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

Inventor： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

Abstract translation: 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

公开(公告)号：US07297994B2

公开(公告)日：2007-11-20

申请号：US11072142

申请日：2005-03-04

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H10L29/00 ,  H01L29/80

CPC classification number: H01L21/823807 ,  H01L29/1033 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/6659

Abstract: An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so that the finally obtained dopant concentration in the channel layer is significantly reduced compared to a conventional device to thereby provide a retrograde dopant profile in a channel region of a field effect transistor. Additionally, a barrier diffusion layer may be provided between the well structure and the channel layer to reduce up-diffusion during any heat treatments carried out after the formation of the channel layer. The final dopant profile in the channel region may be adjusted by the thickness of the channel layer, the thickness and the composition of the diffusion barrier layer and any additional implantation steps to introduce dopant atoms in the channel layer.

Abstract translation: 在离子注入步骤之后在阱结构上提供外延生长的沟道层，并且进行热处理步骤以在阱结构中建立所需的掺杂剂分布。 根据需要，沟道层可以是未掺杂的或稍微掺杂的，使得与常规器件相比，沟道层中最终获得的掺杂剂浓度显着降低，从而在场效应晶体管的沟道区域中提供逆向掺杂物分布。 此外，可以在阱结构和沟道层之间提供阻挡扩散层，以在形成沟道层之后进行的任何热处理期间减小向上扩散。 可以通过沟道层的厚度，扩散阻挡层的厚度和组成以及在沟道层中引入掺杂剂原子的任何额外的注入步骤来调整沟道区中的最终掺杂物分布。

公开(公告)号：US20070200176A1

公开(公告)日：2007-08-30

申请号：US11550631

申请日：2006-10-18

Applicant: Thorsten Kammler ,  Patrick Press ,  Rolf Stephan ,  Sven Beyer

Inventor： Thorsten Kammler ,  Patrick Press ,  Rolf Stephan ,  Sven Beyer

IPC: H01L27/12

CPC classification number: H01L29/458 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78687

Abstract: Formation of a silicide layer on the source/drain regions of a field effect transistor with a channel under tensile strain is disclosed. The strain is originated by the silicon/carbon source/drain regions which are grown by CVD deposition. In order to form the silicide layer, a silicon cap layer is deposited in situ by CVD. The silicon cap layer is then employed to form a silicide layer made of a silicon/cobalt compound. This method allows the formation of a silicide cobalt layer in silicon/carbon source/drain regions, which was until the present time not possible.

Abstract translation: 公开了在具有拉伸应变的通道的场效应晶体管的源/漏区上形成硅化物层。 该菌株由通过CVD沉积生长的硅/碳源/漏区产生。 为了形成硅化物层，通过CVD原位沉积硅覆盖层。 然后使用硅覆盖层形成由硅/钴化合物制成的硅化物层。 该方法允许在硅/碳源/漏区中形成硅化钴钴层，直到目前为止不可能。

公开(公告)号：US07217657B2

公开(公告)日：2007-05-15

申请号：US10260926

申请日：2002-09-30

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/4933

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract translation: 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着改善各个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

公开(公告)号：US20060046400A1

公开(公告)日：2006-03-02

申请号：US11114262

申请日：2005-04-26

Applicant: Gert Burbach ,  Rolf Stephan ,  Karsten Wieczorek ,  Manfred Horstmann

Inventor： Gert Burbach ,  Rolf Stephan ,  Karsten Wieczorek ,  Manfred Horstmann

IPC: H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7843

Abstract: A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

Abstract translation: 提供包括第一晶体管元件和第二晶体管元件的半导体结构。 通过在晶体管上形成具有预定应力的应力层来控制第一和第二晶体管元件的沟道区域中的应力。 应力层可以用作通过在晶体管上形成的层间电介质形成接触孔的蚀刻停止层。

公开(公告)号：US06924216B2

公开(公告)日：2005-08-02

申请号：US10440640

申请日：2003-05-19

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L21/265 ,  H01L21/425

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/26513

Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.

Abstract translation: 提出了一种形成场效应晶体管有源区的方法。 根据所提出的方法，可以通过进行两步损伤和非晶化注入工艺来获得卤素结构和源极和漏极区域的浅注入分布。 在第一步骤期间，衬底在第一轻离子注入步骤期间损坏，并且随后在第二重离子注入步骤期间基本上完全非晶化。

公开(公告)号：US06673665B2

公开(公告)日：2004-01-06

申请号：US10210637

申请日：2002-07-31

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L218234

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

Abstract: The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed so as to react with a refractory metal to form a low resistance silicide. The upper portion may be exposed by overetching the dielectric layer deposited to form the sidewall spacers.

Abstract translation: 接收硅化物部分的硅线的表面积增加，以减小诸如栅电极的窄多晶硅线中的线电阻。 侧壁间隔件形成为使得侧壁的上部被暴露以与难熔金属反应以形成低电阻硅化物。 可以通过过蚀刻沉积以形成侧壁间隔物的介电层来暴露上部。

公开(公告)号：US06620718B1

公开(公告)日：2003-09-16

申请号：US09557713

申请日：2000-04-25

Applicant: Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

IPC: H01L213205

CPC classification number: H01L29/66507 ,  H01L29/66545

Abstract: The present invention is directed to a method of forming metal silicide regions on a gate electrode (23) and on the source/drain regions (25) of a semiconductor device (100). In one illustrative embodiment, the method comprises forming a gate stack (17) above a semiconducting substrate (20), the gate stack (17) being comprised of a gate electrode (23) and a protective layer (24), forming a plurality of source/drain regions (25) in the substrate (20), and forming a first metal silicide region (28) above each of the source/drain regions (25). The method further comprises removing the protective layer (24) from above the gate electrode (23) and forming a second metal silicide region (31) above the gate electrode (23).

Abstract translation: 本发明涉及一种在半导体器件（100）的栅电极（23）和源/漏区（25）上形成金属硅化物区的方法。 在一个说明性实施例中，该方法包括在半导体衬底（20）上方形成栅极叠层（17），栅叠层（17）由栅电极（23）和保护层（24）组成，形成多个 源极/漏极区（25），并且在源极/漏极区（25）之上形成第一金属硅化物区（28）。 该方法还包括从栅电极（23）上方去除保护层（24），并在栅电极（23）上方形成第二金属硅化物区域（31）。

公开(公告)号：US08796807B2

公开(公告)日：2014-08-05

申请号：US13251532

申请日：2011-10-03

Applicant: Rolf Stephan ,  Markus Forsberg ,  Gert Burbach ,  Anthony Mowry

Inventor： Rolf Stephan ,  Markus Forsberg ,  Gert Burbach ,  Anthony Mowry

IPC: H01L31/058

CPC classification number: H01L27/0629 ,  H01L21/823807 ,  H01L27/1203

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract translation: 通过将锗材料结合到热敏二极管结构中，其灵敏度可以显着增加。 在一些说明性实施例中，可以与用于将硅/锗材料并入复杂半导体器件的P沟道晶体管的工艺流程具有高兼容性来执行用于并入锗材料的工艺。 因此，可以降低模具面积消耗来提高温度控制效率。

公开(公告)号：US20130075821A1

公开(公告)日：2013-03-28

申请号：US13241915

申请日：2011-09-23

Applicant: Peter Baars ,  Richard Carter ,  Rolf Stephan

Inventor： Peter Baars ,  Richard Carter ,  Rolf Stephan

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/66545 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.

Abstract translation: 当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时，自对准接触开口用适当的填充材料填充，例如多晶硅 而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。 以这种方式，高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。 在一个说明性实施例中，栅电极结构的占位符材料以硅/锗材料的形式提供。