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    Method and apparatus for implementing reduced memory mode for high-definition television
    42.
    发明授权
    Method and apparatus for implementing reduced memory mode for high-definition television 有权
    用于实现高分辨率电视的减少存储模式的方法和装置

    公开(公告)号：US08165220B2

    公开(公告)日：2012-04-24

    申请号：US12356283

    申请日：2009-01-20

    Applicant: Sherman (Xuemin) Chen ,  Jason Demas ,  Sandeep Bhatia

    Inventor： Sherman (Xuemin) Chen ,  Jason Demas ,  Sandeep Bhatia

    IPC: H04N7/12 ,  H04N11/04

    CPC classification number: H04N19/90 ,  H04N19/126 ,  H04N19/159 ,  H04N19/162 ,  H04N19/172 ,  H04N19/174 ,  H04N19/428 ,  H04N19/61

    Abstract: A method and apparatus are provided for implementing an enhanced reduced memory mode (RMM) of decoding HDTV MPEG-2 video stream. In one instance, the RMM mode is adaptively enabled with up/down conversion by using the picture-type information. In another instance, the RMM mode is provided by performing anchor-frame compression/decompression by using adaptive DPCM technique with picture-type information. The quantization (PCM) tables are generated using the Lloyd algorithm. Further, the predictor for each pixel is determined by a use of the Graham rule.

    Abstract translation: 提供了一种用于实现解码HDTV MPEG-2视频流的增强减少存储模式（RMM）的方法和装置。 在一种情况下，RMM模式通过使用图片类型信息自适应地启用上/下转换。 在另一种情况下，通过使用具有图片类型信息的自适应DPCM技术来执行锚帧压缩/解压缩来提供RMM模式。 使用劳埃德算法生成量化（PCM）表。 此外，通过使用Graham规则来确定每个像素的预测器。

    METHOD AND SYSTEM FOR FAST CHANNEL CHANGE BETWEEN PROGRAMS UTILIZING A SINGLE DECODER TO CONCURRENTLY DECODE MULTIPLE PROGRAMS
    43.
    发明申请
    METHOD AND SYSTEM FOR FAST CHANNEL CHANGE BETWEEN PROGRAMS UTILIZING A SINGLE DECODER TO CONCURRENTLY DECODE MULTIPLE PROGRAMS 审中-公开
    使用单个解码器来同时解码多个程序的程序之间的快速通道更改的方法和系统

    公开(公告)号：US20120008053A1

    公开(公告)日：2012-01-12

    申请号：US12857173

    申请日：2010-08-16

    Applicant: Jeffrey Fisher ,  Shivapirakasan Kanakaraj ,  Sandeep Bhatia ,  Subramanian Kuppuswamy ,  Andrew Robinson

    Inventor： Jeffrey Fisher ,  Shivapirakasan Kanakaraj ,  Sandeep Bhatia ,  Subramanian Kuppuswamy ,  Andrew Robinson

    IPC: H04N5/50

    CPC classification number: H04N21/4384 ,  H04L65/4076 ,  H04L65/80 ,  H04N21/4347

    Abstract: A video receiver comprising a single decoder may be operable to decode concurrently, by the single decoder, a plurality of received programs. The plurality of received programs may comprise a current program associated with a current channel and one or more other programs associated with one or more corresponding other channels. The video receiver may be operable to cause display of the decoded current program associated with the current channel for viewing. The plurality of received programs may be received via a single transport stream. The plurality of received programs may be received via a plurality of transport streams. The video receiver may be operable to switch from the current channel to one of the other channels based on a received request. The video receiver may be operable to cause display of one of the decoded other programs which is associated with the switched channel.

    Abstract translation: 包括单个解码器的视频接收器可以被操作以由单个解码器同时解码多个接收的节目。 多个接收到的节目可以包括与当前频道相关联的当前节目以及与一个或多个对应的其他频道相关联的一个或多个其他节目。 视频接收器可以可操作以使得与当前频道相关联的解码的当前节目的显示被查看。 可以经由单个传输流来接收多个接收到的节目。 可以经由多个传输流来接收多个所接收的节目。 视频接收器可以可操作以基于接收到的请求从当前频道切换到其他信道中的一个。 视频接收器可以可操作地引起与切换的频道相关联的解码的其他节目之一的显示。

    Direct memory accessing for fetching macroblocks
    46.
    发明授权
    Direct memory accessing for fetching macroblocks 失效
    用于获取宏块的直接存储器访问

    公开(公告)号：US07889206B2

    公开(公告)日：2011-02-15

    申请号：US10463170

    申请日：2003-06-16

    Applicant: R. Lakshmikanth Pai ,  Ravindra Bidnur ,  Sandeep Bhatia ,  Lakshmanan Ramakrishnan ,  Vijayanand Aralaguppe

    Inventor： R. Lakshmikanth Pai ,  Ravindra Bidnur ,  Sandeep Bhatia ,  Lakshmanan Ramakrishnan ,  Vijayanand Aralaguppe

    IPC: G06F12/00 ,  G06F12/02 ,  G09G5/37

    CPC classification number: G06F13/28 ,  G06F12/04

    Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.

    Abstract translation: 这里呈现的是用于从存储器检索对象的系统，方法和装置。 可以以一种方式存储对象，使得对象的第一个字节和对象的最后一个字节位于存储器数据字的中间。 该对象由直接存储器访问控制器检索。 直接存储器访问控制器当被提供有具有起始地址和对象的结束地址的读取事务时，检索存储对象的数据字，并且覆盖该对象之前和之后的数据字的部分。

    Methods and apparatus for scan testing of integrated circuits with scan registers
    47.
    发明授权
    Methods and apparatus for scan testing of integrated circuits with scan registers 失效
    具有扫描寄存器的集成电路的扫描测试方法和装置

    公开(公告)号：US07743298B1

    公开(公告)日：2010-06-22

    申请号：US12258421

    申请日：2008-10-26

    Applicant: Sandeep Bhatia ,  Oriol Roig

    Inventor： Sandeep Bhatia ,  Oriol Roig

    IPC: G01R31/28

    CPC classification number: G01R31/318541

    Abstract: In one embodiment of the invention, a method of scan testing an integrated circuit is disclosed. The method includes scanning a first test vector and a second test vector sequentially into a plurality of scan registers serially coupled together, each of the plurality of scan registers including a master latch, a scan latch, and a functional latch; and applying the first and the second test vectors sequentially in a delay fault test via the plurality of scan registers to a combinational logic circuit coupled to the plurality of scan registers.

    Abstract translation: 在本发明的一个实施例中，公开了一种集成电路的扫描测试方法。 该方法包括将第一测试向量和第二测试向量顺序地扫描到串联耦合在一起的多个扫描寄存器，多个扫描寄存器中的每一个包括主锁存器，扫描锁存器和功能锁存器; 以及将第一测试向量和第二测试向量顺序地经由多个扫描寄存器的延迟故障测试应用到耦合到所述多个扫描寄存器的组合逻辑电路。

    TEST COMPACTION USING LINEAR-MATRIX DRIVEN SCAN CHAINS
    48.
    发明申请
    TEST COMPACTION USING LINEAR-MATRIX DRIVEN SCAN CHAINS 失效
    使用线性矩阵驱动扫描链的测试压缩

    公开(公告)号：US20100058129A1

    公开(公告)日：2010-03-04

    申请号：US12549951

    申请日：2009-08-28

    Applicant: Sandeep Bhatia

    Inventor： Sandeep Bhatia

    IPC: G01R31/3177 ,  G06F11/25

    CPC classification number: G01R31/318547

    Abstract: A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.

    Abstract translation: 使用线性矩阵驱动扫描链的扫描技术以及ATPG，以通过线性矩阵生成约束扫描测试向量。 线性矩阵扫描技术将测试应用时间和测试矢量数量与常规技术相比降低了几个数量级，而不会降低故障覆盖。

    Method and system for clock skew independent scan register chains
    49.
    发明授权
    Method and system for clock skew independent scan register chains 失效
    时钟偏移独立扫描寄存器链的方法和系统

    公开(公告)号：US07613969B2

    公开(公告)日：2009-11-03

    申请号：US11081315

    申请日：2005-03-16

    Applicant: Sandeep Bhatia

    Inventor： Sandeep Bhatia

    IPC: G01R31/28 ,  H03K3/289

    CPC classification number: G01R31/318541 ,  G01R31/318594

    Abstract: A method and system for clock skew independent scan chains. In one embodiment, a method comprises connecting a plurality of mux-D scan registers in a chain configuration, wherein a first mux-D scan register of the plurality is associated with a first clock network, and a second mux-D scan register of the plurality is associated with a second clock network. The plurality of mux-D scan registers have a scan mode. The first mux-D scan register and the second mux-D scan register become clock skew independent by controlling a scan-enable signal and a clock signal.

    Abstract translation: 一种用于时钟偏移独立扫描链的方法和系统。 在一个实施例中，一种方法包括以链式配置连接多个多路复用D扫描寄存器，其中多个第一多路复用D扫描寄存器与第一时钟网络相关联，以及第二多路复用D扫描寄存器 多个与第二时钟网络相关联。 多个多路复用D扫描寄存器具有扫描模式。 通过控制扫描使能信号和时钟信号，第一个mux-D扫描寄存器和第二个m-D扫描寄存器变得与时钟偏移无关。

    Test compaction using linear-matrix driven scan chains
    50.
    发明授权
    Test compaction using linear-matrix driven scan chains 有权
    使用线性矩阵驱动扫描链进行测试压实

    公开(公告)号：US07584392B2

    公开(公告)日：2009-09-01

    申请号：US10630537

    申请日：2003-07-29

    Applicant: Sandeep Bhatia

    Inventor： Sandeep Bhatia

    IPC: G01R31/28

    CPC classification number: G01R31/318547

    Abstract: A scan technique using linear matrix to drive scan chains is used, along with an ATPG, to constraint scan test vectors to be generated through the linear matrix. The linear matrix scan technique reduces the test application time and the amount of test vector data by several orders of magnitude over conventional techniques, without reducing fault coverage.

    Abstract translation: 使用线性矩阵驱动扫描链的扫描技术以及ATPG，以通过线性矩阵生成约束扫描测试向量。 线性矩阵扫描技术将测试应用时间和测试矢量数量与常规技术相比降低了几个数量级，而不会降低故障覆盖。

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